Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
116 Freescale Semiconductor
2.3.65 Port J Interrupt Flag Register (PIFJ)
2.3.66 Port AD0 Data Register 0 (PT0AD0)
Address 0x026F Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PIFJ7 PIFJ6
0000
PIFJ1 PIFJ0
W
Reset 00000000
Figure 2-63. Port J Interrupt Flag Register (PIFJ)
Table 2-62. PIFJ Register Field Descriptions
Field Description
7-6, 1-0
PIFJ
Port J interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x0270 Access: User read/write
1
1
Read: Anytime, the data source depends on the data direction value
Write: Anytime
76543210
R
PT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00
W
Altern.
Function
AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8
Reset 00000000
Figure 2-64. Port AD0 Data Register 0 (PT0AD0)
Table 2-63. PT0AD0 Register Field Descriptions
Field Description
7-0
PT0AD0
Port AD0 general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.