Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
118 Freescale Semiconductor
2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0)
2.3.70 Port AD0 Reduced Drive Register 0 (RDR0AD0)
Address 0x0273 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
W
Reset 00000000
Figure 2-67. Port AD0 Data Direction Register 1 (DDR1AD0)
Table 2-66. DDR1AD0 Register Field Descriptions
Field Description
7-0
DDR1AD0
Port AD0 data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0274 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00
W
Reset 00000000
Figure 2-68. Port AD0 Reduced Drive Register 0 (RDR0AD0)
Table 2-67. RDR0AD0 Register Field Descriptions
Field Description
7-0
RDR0AD0
Port AD0 reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled