Datasheet

Memory Mapping Control (S12XMMCV4)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 147
3.4.3 Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM )
with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping
operations. All internal resources are connected to specific target buses (see Figure 3-20).
Figure 3-20. MMC Block Diagram
CPU
BDM
Target Bus Controller
DBG
MMC
Address Decoder & Priority
Peripherals
PGMFLASHData FLASH RAM
S12X1
S12X0
XBUS0