Datasheet

Background Debug Module (S12XBDMV2)
S12XS Family Reference Manual Rev. 1.13
Freescale Semiconductor 185
Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
High-Impedance
Earliest
Start of
Next Bit
R-C Rise
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Perceived
Start of Bit Time
BKGD Pin
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
High-Impedance
High-Impedance