Datasheet

S12X Debug (S12XDBGV3) Module
S12XS Family Reference Manual, Rev. 1.13
196 Freescale Semiconductor
6.1.2 Overview
The comparators monitor the bus activity of the CPU12X. When a match occurs the control logic can
trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or
a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
6.1.3 Features
Four comparators (A, B, C, and D)
Comparators A and C compare the full address bus and full 16-bit data bus
Comparators A and C feature a data bus mask register
Comparators B and D compare the full address bus only
Each comparator can be configured to monitor CPU12X buses
Each comparator features selection of read or write access cycles
Comparators B and D allow selection of byte or word access cycles
Comparisons can be used as triggers for the state sequencer
Three comparator modes
Simple address/data comparator match mode
Inside address range mode, Addmin Address Addmax
Outside address range match mode, Address < Addmin or Address > Addmax
Two types of triggers
Tagged — This triggers just before a specific instruction begins execution
Force — This triggers on the first instruction boundary after a match occurs.
The following types of breakpoints
CPU12X breakpoint entering BDM on breakpoint (BDM)
CPU12X breakpoint executing SWI on breakpoint (SWI)
TRIG Immediate software trigger independent of comparators
Four trace modes
Data Line 64-bit data entity
CPU CPU12X module
Tag Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the
execution stage a tag hit occurs.
Table 6-2. Glossary Of Terms (continued)
Term Definition