Datasheet

S12X Debug (S12XDBGV3) Module
S12XS Family Reference Manual, Rev. 1.13
198 Freescale Semiconductor
6.1.5 Block Diagram
Figure 6-1. Debug Module Block Diagram
6.2 External Signal Description
The S12XDBG sub-module features no external signals.
6.3 Memory Map and Registers
6.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 6-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0020 DBGC1
R
ARM
0
reserved BDM
DBGBRK
reserved COMRV
W TRIG
0x0021 DBGSR
R TBF 0 0 0 0 SSF2 SSF1 SSF0
W
0x0022 DBGTCR
R
reserved TSOURCE TRANGE TRCMOD TALIGN
W
0x0023 DBGC2
R0000
CDCM ABCM
W
Figure 6-2. Quick Reference to S12XDBG Registers
S12XCPU BUS
TRACE BUFFER
BUS INTERFACE
TRIGGER
MATCH0
STATE
COMPARATOR B
COMPARATOR C
COMPARATOR D
COMPARATOR A
STATE SEQUENCER
MATCH1
MATCH2
MATCH3
TRACE
READ TRACE DATA (DBG READ DATA BUS)
CONTROL
SECURE
BREAKPOINT REQUESTS
COMPARATOR
MATCH CONTROL
TRIGGER
TAG &
TRIGGER
CONTROL
LOGIC
TAG S
TAGHITS
STATE
S12XCPU