Datasheet

S12X Debug (S12XDBGV3) Module
S12XS Family Reference Manual Rev. 1.13
Freescale Semiconductor 201
6.3.2.2 Debug Status Register (DBGSR)
Read: Anytime
Write: Never
3
DBGBRK
S12XDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
to S12XCPU upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated
on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please
refer to Section 6.4.7 for further details.
0 No breakpoint on trigger.
1 Breakpoint on trigger
1–0
COMRV
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See Table 6-5.
Table 6-5. COMRV Encoding
COMRV Visible Comparator Visible Register at 0x0027
00 Comparator A DBGSCR1
01 Comparator B DBGSCR2
10 Comparator C DBGSCR3
11 Comparator D DBGMFR
Address: 0x0021
76543210
R TBF 0 0 0 0 SSF2 SSF1 SSF0
W
Reset
POR
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-4. Debug Status Register (DBGSR)
Table 6-6. DBGSR Field Descriptions
Field Description
7
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit.
2–0
SSF[2:0]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-7
.
Table 6-4. DBGC1 Field Descriptions (continued)
Field Description