Datasheet

S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 237
Chapter 8
S12XE Clocks and Reset Generator (S12XECRGV1)
8.1 Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
8.1.1 Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
• System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
• Computer Operating Properly (COP) watchdog timer with time-out clear window.
Table 8-1. Revision History
Revision
Number
Revision
Date
Sections
Affected
Description of Changes
V01.00 26 Oct. 2005 Initial release
V01.01 02 Nov 2006 8.4.1.1/8-254 Table “Examples of IPLL Divider settings”: corrected $32 to $31
V01.02 4 Mar. 2008
8.4.1.4/8-257
8.4.3.3/8-261
Corrected details
V01.03 1 Sep. 2008 Table 8-14 added 100MHz example for PLL
V01.04 20 Nov. 2008 8.3.2.4/8-243 S12XECRG Flags Register: corrected address to Module Base + 0x0003
V01.05 19. Sep 2009 8.5.1/8-263 Modified Note below Table 8-17./8-263
V01.06 18. Sep 2012
Table 8-14
8.5.1
Added footnote concerning maximum clock frequencies to table
Removed redundant examples from table
Replaced reference to MMC documentation