Datasheet

Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.13
276 Freescale Semiconductor
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000 ATDCTL0
R
Reserved
000
WRAP3 WRAP2 WRAP1 WRAP0
W
0x0001 ATDCTL1
R
ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0002 ATDCTL2
R0
AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
W
0x0003 ATDCTL3
R
DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
0x0004 ATDCTL4
R
SMP2 SMP1 SMP0 PRS[4:0]
W
0x0005 ATDCTL5
R0
SC SCAN MULT CD CC CB CA
W
0x0006 ATDSTAT0
R
SCF
0
ETORF FIFOR
CC3 CC2 CC1 CC0
W
0x0007
Unimple-
mented
R0 000 0 0 0 0
W
0x0008 ATDCMPEH
R
CMPE[15:8]
W
0x0009 ATDCMPEL
R
CMPE[7:0]
W
0x000A ATDSTAT2H
R CCF[15:8]
W
0x000B ATDSTAT2L
R CCF[7:0]
W
0x000C ATDDIENH
R
IEN[15:8]
W
0x000D ATDDIENL
R
IEN[7:0]
W
0x000E ATDCMPHTH
R
CMPHT[15:8]
W
0x000F ATDCMPHTL
R
CMPHT[7:0]
W
0x0010 ATDDR0
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0012 ATDDR1
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0014 ATDDR2
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0016 ATDDR3
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0018 ATDDR4
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001A ATDDR5
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001C ATDDR6
R
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
= Unimplemented or Reserved
Figure 10-3. ADC12B16C Register Summary (Sheet 1 of 2)