Datasheet

Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 279
Table 10-4. ATDCTL1 Field Descriptions
Field Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 10-6.
6–5
SRES[1:0]
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 10-5 for
coding.
4
SMP_DIS
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
ETRIGCH[3:0]
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in Table 10-6.
Table 10-5. A/D Resolution Coding
SRES1 SRES0 A/D Resolution
0 0 8-bit data
0 1 10-bit data
1 0 12-bit data
1 1 Reserved
Table 10-6. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
0 0 0 0 0 AN0
0 0 0 0 1 AN1
0 0 0 1 0 AN2
0 0 0 1 1 AN3
0 0 1 0 0 AN4
0 0 1 0 1 AN5
0 0 1 1 0 AN6
0 0 1 1 1 AN7
0 1 0 0 0 AN8
0 1 0 0 1 AN9
0 1 0 1 0 AN10
0 1 0 1 1 AN11
0 1 1 0 0 AN12
0 1 1 0 1 AN13
0 1 1 1 0 AN14
0 1 1 1 1 AN15
1 0 0 0 0 ETRIG0
1
1 0 0 0 1 ETRIG1
1