Datasheet

Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.13
28 Freescale Semiconductor
Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values.
A CPU access to any unimplemented space causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block
sizes are listed in Table 1-2.
Table 1-2. Derivative Dependent Memory Parameters of Device Internal Resources
1.1.6 Detailed Register Map
The detailed register map is listed in the appendix of the reference manual.
1.1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID
number and Mask Set number.
The Version ID is a word located in a flash information row at 0x40_00E8. The version ID number
indicates a specific version of internal NVM variables used to patch NVM errata. The default is no patch
(0xFFFF).
Device FLASH_LOW
SIZE/
PPAGE
1
1
Number of 16K pages addressable via PPAGE register
RAM_LOW
SIZE/
RPAGE
2
2
Number of 4K pages addressing the RAM via PPAGE register
DF_HIGH
SIZE/
EPAGE
3
3
Number of 1K pages addressing the DFLASH via the EPAGE register starting upwards from 0x00
S12XS256 0x7C_0000 256K / 16 0x0F_D000 12K / 3 0x10_1FFF 8K / 8
S12XS128 0x7E_0000 128K / 8 0x0F_E000 8K / 2 0x10_1FFF 8K / 8
S12XS64 0x7F_0000 64K / 4 0x0F_F000 4K / 1 0x10_0FFF 4K / 4
Table 1-3. Assigned Part ID Numbers
Device Mask Set Number Part ID
1
1
The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
Version ID
MC9S12XS256 0M05M $C0C0 0xFFFF
MC9S12XS128 0M04M $C1C0 0xFFFF
1M04M $C1C1 0xFFFF
MC9S12XS64 0M04M $C1C0 0xFFFF
1M04M $C1C1 0xFFFF