Datasheet

Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.13
48 Freescale Semiconductor
1.3 System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-6 shows the clock connections from the CRG to all modules.
Consult the S12XECRG section for details on clock generation.
NOTE
The XS family uses the XE family clock and reset generator module.
Therefore all CRG references are related to S12XECRG.
Figure 1-6. Clock Connections
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator
SCI0 . . SCI 1
SPI0
ATD0
CAN0
CRG
Bus Clock
EXTAL
XTAL
Core Clock
Oscillator Clock
RAM S12X FLASH
PIT
TIM
PIM
PWM