Datasheet

Voltage Regulator (S12VREGL3V3V1)
S12XS Family Reference Manual, Rev. 1.13
496 Freescale Semiconductor
17.3.2.2 Control Register (VREGCTRL)
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
0x02F1
76543210
R00000LVDS
LVIE LVIF
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 17-2. Control Register (VREGCTRL)
Table 17-5. VREGCTRL Field Descriptions
Field Description
2
LVDS
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
DDA
is above level V
LVID
or RPM or shutdown mode.
1 Input voltage V
DDA
is below level V
LVIA
and FPM.
1
LVIE
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
0
LVIF
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.