Datasheet

Voltage Regulator (S12VREGL3V3V1)
S12XS Family Reference Manual, Rev. 1.13
500 Freescale Semiconductor
The period can be calculated as follows depending of APICLK:
Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period
Table 17-10. Selectable Autonomous Periodical Interrupt Periods
APICLK APIR[15:0] Selected Period
0 0000 0.2 ms
1
1
When trimmed within specified accuracy. See electrical specifications for details.
0 0001 0.4 ms
1
0 0002 0.6 ms
1
0 0003 0.8 ms
1
0 0004 1.0 ms
1
0 0005 1.2 ms
1
0 ..... .....
0 FFFD 13106.8 ms
1
0 FFFE 13107.0 ms
1
0 FFFF 13107.2 ms
1
1 0000 2 * bus clock period
1 0001 4 * bus clock period
1 0002 6 * bus clock period
1 0003 8 * bus clock period
1 0004 10 * bus clock period
1 0005 12 * bus clock period
1 ..... .....
1 FFFD 131068 * bus clock period
1 FFFE 131070 * bus clock period
1 FFFF 131072 * bus clock period