Datasheet

Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.13
52 Freescale Semiconductor
I-bit maskable service request is a configuration register. It selects if the service request is enabled and the
service request priority level.
Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)
Vector Address
1
Interrupt Source
CCR
Mask
Local Enable
STOP
Wake up
WAIT
Wake up
Vector base + $F8 Unimplemented instruction trap None None — —
Vector base+ $F6 SWI None None — —
Vector base+ $F4 XIRQ X Bit None Yes Yes
Vector base+ $F2
IRQ I bit IRQCR (IRQEN) Yes Yes
Vector base+ $F0 Real time interrupt I bit CRGINT (RTIE) Refer to CRG
interrupt section
Vector base+ $EE TIM timer channel 0 I bit TIE (C0I) No Yes
Vector base + $EC TIM timer channel 1 I bit TIE (C1I) No Yes
Vector base+ $EA TIM timer channel 2 I bit TIE (C2I) No Yes
Vector base+ $E8 TIM timer channel 3 I bit TIE (C3I) No Yes
Vector base+ $E6 TIM timer channel 4 I bit TIE (C4I) No Yes
Vector base+ $E4 TIM timer channel 5 I bit TIE (C5I) No Yes
Vector base + $E2 TIM timer channel 6 I bit TIE (C6I) No Yes
Vector base+ $E0 TIM timer channel 7 I bit TIE (C7I) No Yes
Vector base+ $DE TIM timer overflow I bit TSRC2 (TOF) No Yes
Vector base+ $DC TIM Pulse accumulator A overflow I bit PACTL (PAOVI) No Yes
Vector base + $DA TIM Pulse accumulator input edge I bit PACTL (PAI) No Yes
Vector base + $D8 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes
Vector base+ $D6 SCI0 I bit SCI0CR2
(TIE, TCIE, RIE, ILIE)
Ye s Ye s
Vector base + $D4 SCI1 I bit SCI1CR2
(TIE, TCIE, RIE, ILIE)
Ye s Ye s
Vector base + $D2 ATD0 I bit ATD0CTL2 (ASCIE) Yes Yes
Vector base + $D0
Reserved
Vector base + $CE Port J I bit PIEJ (PIEJ7-PIEJ0) Yes Yes
Vector base + $CC Port H I bit PIEH (PIEH7-PIEH0) Yes Yes
Vector base + $CA
Reserved
Vector base + $C8
Reserved
Vector base + $C6 CRG PLL lock I bit CRGINT(LOCKIE) Refer to CRG
interrupt section
Vector base + $C4 CRG self-clock mode I bit CRGINT (SCMIE) Refer to CRG
interrupt section
Vector base + $C2
to
Vector base + $BC
Reserved