Datasheet

256 KByte Flash Module (S12XFTMR256K1V1)
S12XS Family Reference Manual, Rev. 1.13
532 Freescale Semiconductor
18.3.2.13 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
All bits in the FRSV1 register read 0 and are not writable.
18.3.2.14 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 18.3.2.4). Once ECC fault information has been stored, no other
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
All FECCR bits are readable but not writable.
Offset Module Base + 0x000D
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 18-19. Flash Reserved1 Register (FRSV1)
Offset Module Base + 0x000E
76543210
R ECCR[15:8]
W
Reset 00000000
= Unimplemented or Reserved
Figure 18-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
76543210
R ECCR[7:0]
W
Reset 00000000
= Unimplemented or Reserved
Figure 18-21. Flash ECC Error Results Low Register (FECCRLO)