Datasheet

Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.13
54 Freescale Semiconductor
1.6.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.6.3.4 Memory
The RAM arrays are not initialized out of reset.
1.6.3.5 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded from the Flash
register FOPT. See Table 1-11 and Table 1-12 for coding. The FOPT register is loaded from the Flash
configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any
reset into Special Single Chip mode.
Table 1-11. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Table 1-12. Initial WCOP Configuration
NV[3] in
FOPT Register
WCOP in
COPCTL Register
10
01