Datasheet

Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.13
56 Freescale Semiconductor
1.9 BDM Clock Configuration
The BDM alternate clock source is the oscillator clock.
1.10 Oscillator Configuration
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used.
The
XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
• Power on reset or low-voltage reset
• Clock monitor reset
• Any reset while in self-clock mode or full stop mode