Datasheet

128 KByte Flash Module (S12XFTMR128K1V1)
S12XS Family Reference Manual, Rev. 1.13
566 Freescale Semiconductor
19.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
0x0010
FOPT
R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
W
0x0011
FRSV2
R00000000
W
0x0012
FRSV3
R00000000
W
0x0013
FRSV4
R00000000
W
= Unimplemented or Reserved
Offset Module Base + 0x0000
76543210
R FDIVLD
FDIV[6:0]
W
Reset 00000000
= Unimplemented or Reserved
Figure 19-5. Flash Clock Divider Register (FCLKDIV)
Table 19-6. FCLKDIV Field Descriptions
Field Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
6–0
FDIV[6:0]
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 19-7 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 19.4.1, “Flash Command Operations,” for more information.
Address
& Name
76543210
Figure 19-4. FTMR128K1 Register Summary (continued)