Datasheet

64 KByte Flash Module (S12XFTMR64K1V1)
S12XS Family Reference Manual, Rev. 1.13
632 Freescale Semiconductor
20.3.2.12 Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
All bits in the FRSV0 register read 0 and are not writable.
20.3.2.13 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
All bits in the FRSV1 register read 0 and are not writable.
20.3.2.14 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 20.3.2.4). Once ECC fault information has been stored, no other
011
HI Data 1 [15:8]
LO Data 1 [7:0]
100
HI Data 2 [15:8]
LO Data 2 [7:0]
101
HI Data 3 [15:8]
LO Data 3 [7:0]
Offset Module Base + 0x000C
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 20-18. Flash Reserved0 Register (FRSV0)
Offset Module Base + 0x000D
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 20-19. Flash Reserved1 Register (FRSV1)
Table 20-24. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode)