Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 67
H 0x0260 PTH—Port H Data Register R/W 0x00 2.3.50/2-108
0x0261 PTIH—Port H Input Register R
4
2.3.51/2-109
0x0262 DDRH—Port H Data Direction Register R/W 0x00 2.3.52/2-109
0x0263 RDRH—Port H Reduced Drive Register R/W 0x00 2.3.53/2-110
0x0264 PERH—Port H Pull Device Enable Register R/W 0x00 2.3.54/2-110
0x0265 PPSH—Port H Polarity Select Register R/W 0x00 2.3.55/2-111
0x0266 PIEH—Port H Interrupt Enable Register R/W 0x00 2.3.56/2-111
0x0267 PIFH—Port H Interrupt Flag Register R/W 0x00 2.3.57/2-112
J 0x0268 PTJ—Port J Data Register R/W 0x00 2.3.58/2-112
0x0269 PTIJ—Port J Input Register R
4
2.3.59/2-113
0x026A DDRJ—Port J Data Direction Register R/W 0x00 2.3.60/2-113
0x026B RDRJ—Port J Reduced Drive Register R/W 0x00 2.3.61/2-114
0x026C PERJ—Port J Pull Device Enable Register R/W 0xFF 2.3.62/2-114
0x026D PPSJ—Port J Polarity Select Register R/W 0x00 2.3.63/2-115
0x026E PIEJ—Port J Interrupt Enable Register R/W 0x00 2.3.64/2-115
0x026F PIFJ—Port J Interrupt Flag Register R/W 0x00 2.3.65/2-116
AD 0x0270 PT0AD0—Port AD0 Data Register 0 R/W 0x00 2.3.66/2-116
0x0271 PT1AD0—Port AD0 Data Register 1 R/W 0x00 2.3.67/2-117
0x0272 DDR0AD0—Port AD0 Data Direction Register 0 R/W 0x00 2.3.68/2-117
0x0273 DDR1AD0—Port AD0 Data Direction Register 1 R/W 0x00 2.3.69/2-118
0x0274 RDR0AD0—Port AD0 Reduced Drive Register 0 R/W 0x00 2.3.70/2-118
0x0275 RDR1AD0—Port AD0 Reduced Drive Register 1 R/W 0x00 2.3.71/2-119
0x0276 PER0AD0—Port AD0 Pull Up Enable Register 0 R/W 0x00 2.3.72/2-119
0x0277 PER1AD0—Port AD0 Pull Up Enable Register 1 R/W 0x00 2.3.73/2-120
0x0278
:
0x027F
PIM Reserved R 0x00 2.3.74/2-120
1
Write access not applicable for one or more register bits. Refer to register description.
2
Refer to memory map in SoC Guide to determine related module.
3
Mode dependent.
4
Read always returns logic level on pins.
Table 2-2. Block Memory Map (continued)
Port
Offset or
Address
Register Access Reset Value Section/Page