Datasheet

Electrical Characteristics
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 695
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Figure A-7. SPI Master Timing (CPHA = 1)
In Table A-27 the timing characteristics for master mode are listed.
Table A-27. SPI Master Mode Timing Characteristics
Num C Characteristic Symbol Min Typ Max Unit
1 D SCK frequency f
sck
1/2048 — 1/2
1
1
See Figure A-8.
f
bus
1 D SCK period t
sck
2 — 2048 t
bus
2 D Enable lead time t
lead
— 1/2 — t
sck
3 D Enable lag time t
lag
— 1/2 — t
sck
4 D Clock (SCK) high or low time t
wsck
— 1/2 — t
sck
5 D Data setup time (inputs) t
su
8——ns
6 D Data hold time (inputs) t
hi
8——ns
9 D Data valid after SCK edge t
vsck
— — 29 ns
10 D Data valid after
SS fall (CPHA = 0) t
vss
— — 15 ns
11 D Data hold time (outputs) t
ho
20 — — ns
12 D Rise and fall time inputs t
rfi
—— 8 ns
13 D Rise and fall time outputs t
rfo
—— 8 ns
SCK
(Output)
SCK
(Output)
MISO
(Input)
MOSI
(Output)
1
5 6
MSB IN2
Bit MSB-1. . . 1
LSB IN
Master MSB OUT2
Master LSB OUT
Bit MSB-1. . . 1
4
4
9
12 13
11
Port Data
(CPOL = 0)
(CPOL = 1)
Port Data
SS
(Output)
2
12 13 3
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.