Datasheet

Electrical Characteristics
S12XS Family Reference Manual, Rev. 1.13
696 Freescale Semiconductor
Figure A-8. Derating of maximum f
SCK
to f
bus
ratio in Master Mode
A.8.2 Slave Mode
In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
Figure A-9. SPI Slave Timing (CPHA = 0)
1/2
1/4
f
SCK
/f
bus
f
bus
[MHz]
10 20 30 40
15 25 355
SCK
(Input)
SCK
(Input)
MOSI
(Input)
MISO
(Output)
SS
(Input)
1
9
5 6
MSB IN
Bit MSB-1 . . . 1
LSB IN
Slave MSB
Slave LSB OUT
Bit MSB-1. . . 1
11
4
4
2
7
(CPOL = 0)
(CPOL = 1)
3
13
NOTE: Not defined
12
12
11
See
13
Note
8
10
See
Note