Datasheet

PCB Layout Guidelines
S12XS Family Reference Manual, Rev. 1.13
708 Freescale Semiconductor
Appendix C
PCB Layout Guidelines
C.1 General
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins .
• Central point of the ground star should be the VSS3 pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
• VSSPLL must be directly connected to VSS3.
• Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for C7,
C8, and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
Example layouts are illustrated on the following pages.
Table C-1. Recommended Decoupling Capacitor Choice
Component Purpose Type Value
C1 V
DDF
filter capacitor Ceramic X7R 220 nF
C2 N/A — —
C3 V
DDX2
filter capacitor X7R/tantalum >=100 nF
C4 V
DDPLL
filter capacitor Ceramic X7R 220 nF
C5 OSC load capacitor From crystal manufacturer
C6 OSC load capacitor
C7 V
DDR
filter capacitor X7R/tantalum >=100 nF
C8 N/A — —
C9 V
DD
filter capacitor Ceramic X7R 220 nF
C10 V
DDA1
filter capacitor Ceramic X7R >=100 nF
C11 V
DDX1
filter capacitor X7R/tantalum >=100 nF
Q1 Quartz — —