Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
82 Freescale Semiconductor
2.3.13 PIM Reserved Register
Table 2-12. ECLKCTL Register Field Descriptions
Field Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
6
NCLKX2
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
5
DIV16
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
4-0
EDIV
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3
...
11111 ECLK rate = bus clock rate divided by 32
Address 0x001D (PRR) Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-11. PIM Reserved Register