Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 83
2.3.14 IRQ Control Register (IRQCR)
2.3.15 PIM Reserved Register PIMTEST
1
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Writing to this register when in special modes can alter the pin functionality.
Address 0x001E Access: User read/write
1
1
Read: See individual bit descriptions below
Write: See individual bit descriptions below
76543210
R
IRQE IRQEN
000000
W
Reset 01000000
= Unimplemented or Reserved
Figure 2-12. IRQ Control Register (IRQCR)
Table 2-13. IRQCR Register Field Descriptions
Field Description
7
IRQE
IRQ select edge sensitive only—
Special mode: Read or write anytime
Normal mode: Read anytime, write once
1
IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1
and will be cleared only upon a reset or the servicing of the
IRQ interrupt.
0
IRQ configured for low level recognition.
6
IRQEN
IRQ enable—
Read or write anytime
1
IRQ pin is connected to interrupt logic.
0
IRQ pin is disconnected from interrupt logic.
1. Implementation pim_xe.01.01 and later
Address 0x001F Access: User read
1
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-13. PIM Reserved Register