Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 87
2.3.20 Port T Data Direction Register (DDRT)
2.3.21 Port T Reduced Drive Register (RDRT)
Address 0x0242 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 00000000
Figure 2-18. Port T Data Direction Register (DDRT)
Table 2-18. DDRT Register Field Descriptions
Field Description
7-6, 4
DDRT
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin configured as output
0 Associated pin configured as input
5
DDRT
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the VREG_API forces the I/O state to
be an output if enabled. In these cases the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
3-0
DDRT
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0243 Access: User read/write
1
76543210
R
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W
Reset 00000000
Figure 2-19. Port T Reduced Drive Register (RDRT)