Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 93
2.3.28 Port S Data Direction Register (DDRS)
Table 2-24. PTIS Register Field Descriptions
Field Description
7-0
PTIS
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0249 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
Reset 00000000
Figure 2-26. Port S Data Direction Register (DDRS)
Table 2-25. DDRS Register Field Descriptions
Field Description
7-4
DDRS
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
3-2
DDRS
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI1 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
1-0
DDRS
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input