Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 16-Bit 40 MHz I/O number 44

HCS12

Microcontrollers

freescale.com

MC9S12XS256

Reference Manual

Covers MC9S12XS Family

MC9S12XS256

MC9S12XS128

MC9S12XS64

MC9S12XS256RMV1

Rev. 1.13

08/2012

Summary of content (738 pages)

PAGE 1
MC9S12XS256 Reference Manual Covers MC9S12XS Family MC9S12XS256 MC9S12XS128 MC9S12XS64 HCS12 Microcontrollers MC9S12XS256RMV1 Rev. 1.13 08/2012 freescale.
PAGE 2
To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to freescale.com. This document contains information for the complete S12XS Family and thus includes a set of separate flash (FTMR) module sections to cover the whole family. A full list of family members and options is included in the appendices.
PAGE 3
Chapter 1 Device Overview S12XS Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Chapter 2 Port Integration Module (S12XSPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Chapter 3 Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . . . . . . . . . .127 Chapter 4 Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Chapter 5 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . . . . .
PAGE 4
S12XS Family Reference Manual, Rev. 1.
PAGE 5
Chapter 1 Device Overview S12XS Family 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.3 Block Diagram . . . . . . . . . . . .
PAGE 6
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.3.17 2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
2.4 2.5 2.3.46 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.3.47 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.3.48 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.3.49 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.3.
PAGE 8
3.2 3.3 3.4 3.5 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
5.4 5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
7.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) 8.1 8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 8.1.
PAGE 11
10.2 10.3 10.4 10.5 10.6 10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 10.1.4 Block Diagram of Input structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 10.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . .
PAGE 12
.2 12.3 12.4 12.5 12.6 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 External Signal Description . . . . . . . . . . . . . . . . . . . . . .
PAGE 13
14.2 14.3 14.4 14.5 14.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 14.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 14
15.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 15.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Chapter 16 Timer Module (TIM16B8CV2) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.1.1 Features . . . . . . . . . . . . . . . . . . . .
PAGE 15
17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.7 VREGEN — Optional Regulator Enable Pin . . . . . .
PAGE 16
Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 19.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 19.1.3 Block Diagram . .
PAGE 17
Appendix A Electrical Characteristics A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 A.1.3 Pins . . . . . . . . . . . . . . . . . . . .
PAGE 18
C.1.2 80-Pin QFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 C.1.3 64-Pin LQFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Appendix D Derivative Differences D.1 Memory Sizes and Package Options S12XS family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 Appendix E Detailed Register Address Map E.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 19
Chapter 1 Device Overview S12XS Family 1.1 Introduction The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family. These families provide an easy approach to develop common platforms from low-end to high-end applications, minimizing the redesign of software and hardware.
PAGE 20
Device Overview S12XS Family • • • • • • • • INT (interrupt module) — Seven levels of nested interrupts — Flexible assignment of interrupt sources to each interrupt level.
PAGE 21
Device Overview S12XS Family • • • • – 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure correction and double fault detection – Erase sector size 256 bytes – Automated program and erase algorithm — 4, 8 and 12 Kbyte RAM 16-channel, 12-bit Analog-to-Digital converter — 8/10/12 Bit resolution — 3µs, 10-bit single conversion time — Left or right justified result data — External and internal conversion trigger capability — Internal oscillator for conversion in Stop mod
PAGE 22
Device Overview S12XS Family • • • • • • • — Time-out interrupt and peripheral triggers — Start of timers can be aligned Up to 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator — Programmable period and duty cycle per channel — Center- or left-aligned outputs — Programmable clock select logic with a wide range of frequencies Serial Peripheral Interface Module (SPI) — Configurable for 8 or 16-bit data size — Full-duplex or single-wire bidirectional — Double-buffered transmit and receive —
PAGE 23
Device Overview S12XS Family • 1.1.2 — 64-pin low-profile quad flat-pack (LQFP) Operating Conditions — Wide single Supply Voltage range 3.135 V to 5.
PAGE 24
Device Overview S12XS Family 1.1.3 Block Diagram Figure 1-1 shows a block diagram of the S12XS Family devices CPU12X BKGD EXTAL XTAL Debug Module Single-wire Background 4 address breakpoints Debug Module 2 data breakpoints 512 Byte Trace Buffer Amplitude Controlled Low Power Pierce or Full drive Pierce Oscillator PLL with Frequency Modulation option RESET TEST PTE XIRQ IRQ PTA PB[7:0] PK[7,5:0] PIT 4ch 24-bit Timer Multilevel Interrupt Module CAN0 msCAN 2.
PAGE 25
Device Overview S12XS Family 1.1.4 Device Memory Map Table 1-1 shows the device register memory map. Table 1-1.
PAGE 26
Device Overview S12XS Family Table 1-1. Device Register Memory Map (continued) Address 0x0368–0x07FF Module Reserved Size (Bytes) 1176 NOTE Reserved register space shown in Table 1-1 is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. 1.1.5 Address Mapping Figure 1-2 shows S12XS CPU and BDM local address translation to the global memory map.
PAGE 27
Device Overview S12XS Family CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS Unimplemented RAM 0x0000 0x0800 0x0C00 RAM 2K REGISTERS 1K DFLASH window EPAGE RAMSIZE RAM_LOW 0x0F_FFFF Reserved DFLASH 0x1000 RPAGE 4K RAM window DF_HIGH 0x2000 DFLASH Resources 8K RAM 0x4000 0x13_FFFF Unpaged 16K FLASH Unimplemented Space 0x8000 16K FLASH window PPAGE 0x3F_FFFF Unimplemented FLASH 0xC000 Unpaged 16K FLASH Vectors FLASH_LOW FLASH FLASHSIZE 0xFFFF 0x7F_
PAGE 28
Device Overview S12XS Family Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values. A CPU access to any unimplemented space causes an illegal address reset. The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block sizes are listed in Table 1-2. Table 1-2.
PAGE 29
Device Overview S12XS Family 1.2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device. 1.2.1 Device Pinout The XS family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application.
PAGE 30
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 S12XS Family 112LQFP Pins shown in BOLD are not available on the 80 QFP package VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PAGE 31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PWM4 PP5/KPW5/PWM5 PP7/KPW7/PWM7 VDDX1 VSSX1 PM0/RXCAN0/RXD1 PM1/TXCAN0/TXD1 PM2/MISO0 PM3/SS0 PM4/MOSI0 PM5/SCK0 PJ6/KWJ6 PJ7/KWJ7 TEST PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL Device Overview S12XS Family S12XS Family 80QFP Pins shown in BOLD are not available on the 64 QFP package 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12
PAGE 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PP5/KPW5/PWM5 PP7/KWP7/PWM7 VDDX1 VSSX1 PM0/RXCAN0/RXD1 PM1/TXCAN0/TXD1 PM2/MISO0 PM3/SS0 PM4/MOSI0 PM5/SCK0 TEST PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA/VRL Device Overview S12XS Family 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S12XS Family 64LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD PA3 PA2 PA1 PA0 PB5 PB6 PB7 XCLKS/ECLKX2/PE7 ECLK/PE4 VS
PAGE 33
Device Overview S12XS Family 1.2.2 Pin Assignment Overview Table 1-4 provides a summary of which ports are available for each package option. Routing of pin functions is summarized in Table 1-5. Table 1-4. Port Availability by Package Option Port 112 LQFP 80 QFP 64 LQFP Port AD/ADC Channels 16/16 8/8 8/8 Port A pins 8 8 4 Port B pins 8 8 4 Port E pins inc.
PAGE 34
Table 1-6. Pin-Out Summary1 Package Terminal S12XS Family Reference Manual, Rev. 1.13 LQFP 112 QFP 80 LQFP 64 1 1 2 Function Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 35
Freescale Semiconductor Table 1-6. Pin-Out Summary1 (continued) Package Terminal LQFP 112 QFP 80 LQFP 64 16 12 17 Function S12XS Family Reference Manual, Rev. 1.13 Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 36
Package Terminal LQFP 112 QFP 80 LQFP 64 36 24 37 Function S12XS Family Reference Manual, Rev. 1.13 Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 37
Freescale Semiconductor Table 1-6. Pin-Out Summary1 (continued) Package Terminal LQFP 112 QFP 80 LQFP 64 55 39 56 Function S12XS Family Reference Manual, Rev. 1.13 Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 38
Package Terminal LQFP 112 QFP 80 LQFP 64 72 - 73 Function S12XS Family Reference Manual, Rev. 1.13 Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 39
Freescale Semiconductor Table 1-6. Pin-Out Summary1 (continued) Package Terminal LQFP 112 QFP 80 LQFP 64 87 - 88 Function S12XS Family Reference Manual, Rev. 1.13 Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 40
Package Terminal LQFP 112 QFP 80 LQFP 64 106 76 107 Function S12XS Family Reference Manual, Rev. 1.13 Pin 2nd Func. 3rd Func. 4th Func. 5th Func.
PAGE 41
Device Overview S12XS Family 1.2.3 Detailed Signal Descriptions NOTE The pin list of the largest package version of each S12XS Family derivative gives the complete of interface signals that also exist on smaller package options, although some of them are not bonded out. For devices assembled in smaller packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-6 for affected pins. 1.2.3.
PAGE 42
Device Overview S12XS Family 1.2.3.8 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7 PE7 is a general-purpose input or output pin. ECLKX2 is a clock output of twice the internal bus frequency. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Section 1.10 Oscillator Configuration). An internal pull-up is enabled during reset. 1.2.3.
PAGE 43
Device Overview S12XS Family 1.2.3.18 PM[7:6] — Port M I/O Pins 7-6 PM[7:6] are a general-purpose input or output pins. 1.2.3.19 PM5 / SCK0 — Port M I/O Pin 5 PM5 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). 1.2.3.20 PM4 / MOSI0 — Port M I/O Pin 4 PM4 is a general-purpose input or output pin.
PAGE 44
Device Overview S12XS Family 1.2.3.27 PP2 / KWP2 / PWM2 / TXD1 / IOC2 — Port P I/O Pin 2 PP2 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as pulse width modulator (PWM) channel 2 output, TIM channel 2 or as the transmit pin TXD of serial communication interface 1 (SCI1). 1.2.3.28 PP1 / KWP1 / PWM1 / IOC1 — Port P I/O Pin 1 PP1 is a general-purpose input or output pin. It can be configured as a keypad wakeup input.
PAGE 45
Device Overview S12XS Family 1.2.3.36 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 0 (SCI0). 1.2.3.37 PS0 / RXD0 — Port S I/O Pin 0 PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 0 (SCI0). 1.2.3.38 PT[7:6] / IOC[7:6] / PWM[7:6] — Port T I/O Pins 7-6 PT[7:6] are general-purpose input or output pins.
PAGE 46
Device Overview S12XS Family 1.2.4.3 VDD, VSS2, VSS3 — Core Power Pins The voltage supply of nominally 1.8 V is derived from the internal voltage regulator. The return current path is through the VSS2 and VSS3 pins. No static external loading of these pins is permitted. 1.2.4.4 VDDF, VSS1 — NVM Power Pins The voltage supply of nominally 2.8 V is derived from the internal voltage regulator. The return current path is through the VSS1 pin. No static external loading of these pins is permitted. 1.2.4.
PAGE 47
Device Overview S12XS Family Table 1-7. Power and Ground Connection Summary Mnemonic Nominal Voltage VDDPLL 1.8 V VSSPLL 0V Description Provides operating voltage and ground for the phased-locked loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. S12XS Family Reference Manual, Rev. 1.
PAGE 48
Device Overview S12XS Family 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-6 shows the clock connections from the CRG to all modules. Consult the S12XECRG section for details on clock generation. NOTE The XS family uses the XE family clock and reset generator module. Therefore all CRG references are related to S12XECRG. SCI0 . .
PAGE 49
Device Overview S12XS Family The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 1-6, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals. The program Flash memory is supplied by the bus clock and the oscillator clock. The oscillator clock is used as a time base to derive the program and erase times for the NVMs.
PAGE 50
Device Overview S12XS Family 1.4.1.2 Special Single-Chip Mode This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin. 1.4.2 Power Modes The MCU features two main low-power modes.
PAGE 51
Device Overview S12XS Family 1.4.2.5 Run Mode Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save power. 1.4.3 Freeze Mode The timer module, pulse width modulator, analog-to-digital converters, and the periodic interrupt timer provide a software programmable option to freeze the module status when the background debug module is active. This is useful when debugging application software.
PAGE 52
Device Overview S12XS Family I-bit maskable service request is a configuration register. It selects if the service request is enabled and the service request priority level. Table 1-10.
PAGE 53
Device Overview S12XS Family Table 1-10.
PAGE 54
Device Overview S12XS Family 1.6.3.1 Flash Configuration Reset Sequence Phase On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module section. 1.6.3.
PAGE 55
Device Overview S12XS Family 1.7 1.7.1 ATD0 Configuration External Trigger Input Connection The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-13 shows the connection of the external trigger inputs. Table 1-13.
PAGE 56
Device Overview S12XS Family 1.9 BDM Clock Configuration The BDM alternate clock source is the oscillator clock. 1.10 Oscillator Configuration The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing.
PAGE 57
Device Overview S12XS Family The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above described reset cases. EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 1-7. Loop Controlled Pierce Oscillator Connections (XCLKS = 1) EXTAL C1 MCU RB RS Crystal or Ceramic Resonator XTAL C2 RB=1MΩ ; RS specified by crystal vendor VSSPLL Figure 1-8.
PAGE 58
Device Overview S12XS Family S12XS Family Reference Manual, Rev. 1.
PAGE 59
Chapter 2 Port Integration Module (S12XSPIMV1) Revision History Revision Number Revision Date V01.07 08 Feb 2011 2.3.55/2-111 2.3.56/2-111 2.3.57/2-112 V01.08 08 Jul 2011 Table 2-2./2-65 V01.09 11 Sep 2012 2.1 2.1.
PAGE 60
Port Integration Module (S12XSPIMV1) NOTE This document assumes the availability of all features (112-pin package option). Some functions are not available on lower pin count package options. Refer to the pin-out summary section. 2.1.
PAGE 61
Port Integration Module (S12XSPIMV1) NOTE If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority) Table 2-1.
PAGE 62
Port Integration Module (S12XSPIMV1) Table 2-1. Pin Functions and Priorities (continued) Port Pin Name Pin Function & Priority1 T PT7 IOC7 (PWM7) PT6 I/O Timer Channel 6 I/O General purpose IOC5 I/O Timer Channel 5 PS7 PS6 PS5 IOC4 I/O Timer Channel 4 IOC[3:0] SS0 PS3 PS2 PS1 PS0 O Pulse Width Modulator channel 4 I/O General purpose I/O Timer Channel 3 - 0 I/O General purpose I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode.
PAGE 63
Port Integration Module (S12XSPIMV1) Table 2-1. Pin Functions and Priorities (continued) Port Pin Name Pin Function & Priority1 M PM[7:6] GPIO PM5 (SCK0) GPIO PM4 PM3 PM2 (MOSI0) I/O General purpose I/O Serial Peripheral Interface 0 master out/slave in pin I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode.
PAGE 64
Port Integration Module (S12XSPIMV1) Table 2-1.
PAGE 65
Port Integration Module (S12XSPIMV1) 2.3.1 Memory Map Table 2-2 shows the register map of the Port Integration Module. Table 2-2. Block Memory Map Port A B E A B E K E K Offset or Address Register Access Reset Value Section/Page 0x0000 PORTA—Port A Data Register R/W 0x00 2.3.3/2-75 0x0001 PORTB—Port B Data Register R/W 0x00 2.3.4/2-75 0x0002 DDRA—Port A Data Direction Register R/W 0x00 2.3.5/2-76 0x0003 DDRB—Port B Data Direction Register R/W 0x00 2.3.
PAGE 66
Port Integration Module (S12XSPIMV1) Table 2-2. Block Memory Map (continued) Port Offset or Address T 0x0240 S M P Register Access Reset Value Section/Page PTT—Port T Data Register R/W 0x00 2.3.18/2-85 0x0241 PTIT—Port T Input Register R 4 2.3.19/2-86 0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.3.20/2-87 0x0243 RDRT—Port T Reduced Drive Register R/W 0x00 2.3.21/2-87 0x0244 PERT—Port T Pull Device Enable Register R/W 0x00 2.3.
PAGE 67
Port Integration Module (S12XSPIMV1) Table 2-2. Block Memory Map (continued) Port Offset or Address H 0x0260 J AD Register Access Reset Value Section/Page PTH—Port H Data Register R/W 0x00 2.3.50/2-108 0x0261 PTIH—Port H Input Register R 4 2.3.51/2-109 0x0262 DDRH—Port H Data Direction Register R/W 0x00 2.3.52/2-109 0x0263 RDRH—Port H Reduced Drive Register R/W 0x00 2.3.53/2-110 0x0264 PERH—Port H Pull Device Enable Register R/W 0x00 2.3.
PAGE 68
Port Integration Module (S12XSPIMV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0x0004 R Reserved W 0 0 0 0 0 0 0 0 0x0005 R Reserved W 0 0 0 0 0 0 0 0 0x0006 R Reserved W 0 0 0 0 0 0 0 0 0x0007 R Reserved W 0 0 0 0 0 0 0 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 DDRE7 DDRE6 D
PAGE 69
Port Integration Module (S12XSPIMV1) Register Name 0x001C R ECLKCTL W 0x001D R Reserved W 0x001E IRQCR W 0x001F R Reserved R Bit 7 6 5 4 3 2 1 Bit 0 NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 IRQE IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0020– R 0x0031 W Non-PIM Address Range 0x0032 PORTK 0x0033 DDRK R W R W Non-PIM Address Range PK7 DDRK7 0 0 PK5 PK4 PK3 PK2 PK1 PK0 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 0x0034– R 0x023F W N
PAGE 70
Port Integration Module (S12XSPIMV1) Register Name 0x0246 R Reserved W 0x0247 PTTRR W 0x0248 PTS W 0x0249 PTIS R R R W 0x024B RDRS W R R R W 0x024D PPSS W 0x024E WOMS W R R 0x024F R Reserved W 0x0250 PTM R W 0x0251 PTIM W 0x0252 DDRM W 0x0253 RDRM 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PTTRR7 PTTRR6 PTTRR5 PTTRR4 PTTRR2 PTTRR1 PTTRR0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4
PAGE 71
Port Integration Module (S12XSPIMV1) Register Name 0x0256 WOMM R W 0x0257 MODRR W 0x0258 PTP W 0x0259 PTIP 0x025A DDRP R R R R W W 0x025C PERP W R R R W 0x025E PIEP W 0x025F PIFP W 0x0260 PTH R R R W 0x0261 PTIH W 0x0262 DDRH W 0x0263 RDRH 0x0264 PERH 6 5 4 3 2 1 Bit 0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 MODRR7 MODRR6 0 0 0 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DD
PAGE 72
Port Integration Module (S12XSPIMV1) Register Name 0x0265 PPSH R W 0x0266 PIEH W 0x0267 PIFH W 0x0268 PTJ R R R W 0x0269 PTIJ W 0x026A DDRJ W 0x026B RDRJ R R R W 0x026C PERJ W 0x026D PPSJ W 0x026E PIEJ 0x026F PIFJ R R R W R W 0x0270 PT0AD0 R W 0x0271 PT1AD0 W R Bit 7 6 5 4 3 2 1 Bit 0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 PTJ7 PTJ6 0 0
PAGE 73
Port Integration Module (S12XSPIMV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0275 R RDR1AD0 W RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0x0276 R PER0AD0 W PER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00 0x0277 R PER1AD0 W PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 0x0278 R Reserved W 0 0 0 0 0 0 0 0 0x0279 R Reserved W 0 0 0 0 0 0 0 0 0x027A R Reserved W 0 0 0 0 0 0 0 0 0x0
PAGE 74
Port Integration Module (S12XSPIMV1) Table 2-3.
PAGE 75
Port Integration Module (S12XSPIMV1) 2.3.3 Port A Data Register (PORTA) Access: User read/write1 Address 0x0000 (PRR) 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 R W Reset Figure 2-1. Port A Data Register (PORTA) 1 Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-4.
PAGE 76
Port Integration Module (S12XSPIMV1) 2.3.5 Port A Data Direction Register (DDRA) Access: User read/write1 Address 0x0002 (PRR) 7 6 5 4 3 2 1 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 R W Reset Figure 2-3. Port A Data Direction Register (DDRA) 1 Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-6.
PAGE 77
Port Integration Module (S12XSPIMV1) 2.3.7 PIM Reserved Registers Access: User read1 Address 0x0004 (PRR) to 0x0007 (PRR) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-5. PIM Reserved Registers 1 Read: Always reads 0x00 Write: Unimplemented 2.3.
PAGE 78
Port Integration Module (S12XSPIMV1) Table 2-8. PORTE Register Field Descriptions Field Description 7 PE Port E general purpose input/output data—Data Register, ECLKX2 output, XCLKS input When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
PAGE 79
Port Integration Module (S12XSPIMV1) Table 2-9. DDRE Register Field Descriptions Field 7-2 DDRE Description Port E Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.3.
PAGE 80
Port Integration Module (S12XSPIMV1) Table 2-10. PUCR Register Field Descriptions (continued) Field Description 1 PUPBE Port B Pull-up Enable—Enable pull-up devices on all port input pins This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output this bit has no effect.
PAGE 81
Port Integration Module (S12XSPIMV1) Table 2-11. RDRIV Register Field Descriptions (continued) Field Description 1 RDPB Port B reduced drive—Select reduced drive for output port This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx.
PAGE 82
Port Integration Module (S12XSPIMV1) Table 2-12. ECLKCTL Register Field Descriptions Field Description 7 NECLK No ECLK—Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the internal bus clock. 1 ECLK disabled 0 ECLK enabled 6 NCLKX2 No ECLKX2—Disable ECLKX2 output This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock.
PAGE 83
Port Integration Module (S12XSPIMV1) 2.3.14 IRQ Control Register (IRQCR) Access: User read/write1 Address 0x001E 7 6 IRQE IRQEN 0 1 R 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-12. IRQ Control Register (IRQCR) 1 Read: See individual bit descriptions below Write: See individual bit descriptions below Table 2-13.
PAGE 84
Port Integration Module (S12XSPIMV1) 1 Read: Always reads 0x00 Write: Unimplemented 2.3.16 Port K Data Register (PORTK) Access: User read/write1 Address 0x0032 (PRR) 7 R 6 5 4 3 2 1 0 PK5 PK4 PK3 PK2 PK1 PK0 0 0 0 0 0 0 0 PK7 W Reset 0 0 Figure 2-14. Port K Data Register (PORTK) 1 Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-14.
PAGE 85
Port Integration Module (S12XSPIMV1) Table 2-15. DDRK Register Field Descriptions Field 7,5-0 DDRK Description Port K Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.3.
PAGE 86
Port Integration Module (S12XSPIMV1) Table 2-16. PTT Register Field Descriptions (continued) Field Description 5 PTT Port T general purpose input/output data—Data Register, TIM output, routed PWM output, VREG_API output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
PAGE 87
Port Integration Module (S12XSPIMV1) 2.3.20 Port T Data Direction Register (DDRT) Access: User read/write1 Address 0x0242 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 2-18. Port T Data Direction Register (DDRT) 1 Read: Anytime Write: Anytime Table 2-18. DDRT Register Field Descriptions Field Description 7-6, 4 DDRT Port T data direction— This bit determines whether the pin is an input or output.
PAGE 88
Port Integration Module (S12XSPIMV1) 1 Read: Anytime Write: Anytime Table 2-19. RDRT Register Field Descriptions Field Description 7-0 RDRT Port T reduced drive—Select reduced drive for output pin This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx.
PAGE 89
Port Integration Module (S12XSPIMV1) Table 2-21. PPST Register Field Descriptions Field 7-0 PPST Description Port T pull device select—Configure pull device polarity on input pin This bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 A pull-down device selected 0 A pull-up device selected 2.3.
PAGE 90
Port Integration Module (S12XSPIMV1) Table 2-22. PTTRR Register Field Descriptions Field 7 PTTRR Description Port T peripheral routing— This register controls the routing of PWM channel 7. 1 PWM7 routed to PT7 0 PWM7 routed to PP7 6 PTTRR Port T peripheral routing— This register controls the routing of PWM channel 6. 1 PWM6 routed to PT6 0 PWM6 routed to PP6 5 PTTRR Port T peripheral routing— This register controls the routing of PWM channel 5.
PAGE 91
Port Integration Module (S12XSPIMV1) 2.3.26 Port S Data Register (PTS) Access: User read/write1 Address 0x0248 7 6 5 4 3 2 1 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-24. Port S Data Register (PTS) 1 Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-23.
PAGE 92
Port Integration Module (S12XSPIMV1) Table 2-23. PTS Register Field Descriptions (continued) Field Description 3 PTS Port S general purpose input/output data—Data Register, SCI1 TXD output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
PAGE 93
Port Integration Module (S12XSPIMV1) Table 2-24. PTIS Register Field Descriptions Field Description 7-0 PTIS Port S input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.3.28 Port S Data Direction Register (DDRS) Access: User read/write1 Address 0x0249 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 2-26.
PAGE 94
Port Integration Module (S12XSPIMV1) 2.3.29 Port S Reduced Drive Register (RDRS) Access: User read/write1 Address 0x024A 7 6 5 4 3 2 1 0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 2-27. Port S Reduced Drive Register (RDRS) 1 Read: Anytime Write: Anytime Table 2-26.
PAGE 95
Port Integration Module (S12XSPIMV1) 2.3.31 Port S Polarity Select Register (PPSS) Access: User read/write1 Address 0x024C 7 6 5 4 3 2 1 0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 R W Reset Figure 2-29. Port S Polarity Select Register (PPSS) 1 Read: Anytime Write: Anytime Table 2-28.
PAGE 96
Port Integration Module (S12XSPIMV1) 2.3.33 PIM Reserved Register Access: User read1 Address 0x024F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-31. PIM Reserved Register 1 Read: Always reads 0x00 Write: Unimplemented 2.3.
PAGE 97
Port Integration Module (S12XSPIMV1) Table 2-30. PTM Register Field Descriptions (continued) Field Description 4 PTM Port M general purpose input/output data—Data Register, routed SPI0 MOSI input/output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
PAGE 98
Port Integration Module (S12XSPIMV1) 2.3.35 Port M Input Register (PTIM) Access: User read1 Address 0x0251 R 7 6 5 4 3 2 1 0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 u u u u u u u u W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-33. Port M Input Register (PTIM) 1 Read: Anytime Write:Never, writes to this register have no effect Table 2-31.
PAGE 99
Port Integration Module (S12XSPIMV1) Table 2-32. DDRM Register Field Descriptions Field 7-6 DDRM Description Port M data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 5-2 DDRM Port M data direction— This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output.
PAGE 100
Port Integration Module (S12XSPIMV1) 2.3.38 Port M Pull Device Enable Register (PERM) Access: User read/write1 Address 0x0254 7 6 5 4 3 2 1 0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 0 0 0 0 0 0 0 0 R W Reset Figure 2-36. Port M Pull Device Enable Register (PERM) 1 Read: Anytime Write: Anytime Table 2-34.
PAGE 101
Port Integration Module (S12XSPIMV1) 2.3.40 Port M Wired-Or Mode Register (WOMM) Access: User read/write1 Address 0x0256 7 6 5 4 3 2 1 0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 0 0 0 0 0 0 0 R W Reset Figure 2-38. Port M Wired-Or Mode Register (WOMM) 1 Read: Anytime Write: Anytime Table 2-36.
PAGE 102
Port Integration Module (S12XSPIMV1) Table 2-37. SCI1 Routing MODRRx Related Pins 0 0 PS3 PS2 0 1 PP2 PP0 1 0 PM1 PM0 1 1 Reserved1 Reserved1 1 Defaults to reset value Table 2-38. SPI0 Routing MODRRx 4 2.3.
PAGE 103
Port Integration Module (S12XSPIMV1) Table 2-39. PTP Register Field Descriptions Field Description 7 PTP Port P general purpose input/output data—Data Register, PWM input/output, pin interrupt input/output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
PAGE 104
Port Integration Module (S12XSPIMV1) Table 2-39. PTP Register Field Descriptions (continued) Field Description 1 PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, pin interrupt input/output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
PAGE 105
Port Integration Module (S12XSPIMV1) 2.3.44 Port P Data Direction Register (DDRP) Access: User read/write1 Address 0x025A 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-42. Port P Data Direction Register (DDRP) 1 Read: Anytime Write: Anytime Table 2-41. DDRP Register Field Descriptions Field Description 7 DDRP Port P data direction— This bit determines whether the associated pin is an input or output.
PAGE 106
Port Integration Module (S12XSPIMV1) 2.3.45 Port P Reduced Drive Register (RDRP) Access: User read/write1 Address 0x025B 7 6 5 4 3 2 1 0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-43. Port P Reduced Drive Register (RDRP) 1 Read: Anytime Write: Anytime Table 2-42.
PAGE 107
Port Integration Module (S12XSPIMV1) 2.3.47 Port P Polarity Select Register (PPSP) Access: User read/write1 Address 0x025D 7 6 5 4 3 2 1 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-45. Port P Polarity Select Register (PPSP) 1 Read: Anytime Write: Anytime Table 2-44.
PAGE 108
Port Integration Module (S12XSPIMV1) 2.3.49 Port P Interrupt Flag Register (PIFP) Access: User read/write1 Address 0x025F 7 6 5 4 3 2 1 0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-47. Port P Interrupt Flag Register (PIFP) 1 Read: Anytime Write: Anytime Table 2-46. PIFP Register Field Descriptions Field Description 7-0 PIFP Port P interrupt flag— The flag bit is set after an active edge was applied to the associated input pin.
PAGE 109
Port Integration Module (S12XSPIMV1) 2.3.51 Port H Input Register (PTIH) Access: User read1 Address 0x0261 R 7 6 5 4 3 2 1 0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 u u u u u u u u W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-49. Port H Input Register (PTIH) 1 Read: Anytime Write:Never, writes to this register have no effect Table 2-48.
PAGE 110
Port Integration Module (S12XSPIMV1) 2.3.53 Port H Reduced Drive Register (RDRH) Access: User read/write1 Address 0x0263 7 6 5 4 3 2 1 0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 0 0 0 0 0 0 0 0 R W Reset Figure 2-51. Port H Reduced Drive Register (RDRH) 1 Read: Anytime Write: Anytime Table 2-50.
PAGE 111
Port Integration Module (S12XSPIMV1) 2.3.55 Port H Polarity Select Register (PPSH) Access: User read/write1 Address 0x0265 7 6 5 4 3 2 1 0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 0 0 0 0 0 0 0 0 R W Reset Figure 2-53. Port H Polarity Select Register (PPSH) 1 Read: Anytime Write: Anytime Table 2-52.
PAGE 112
Port Integration Module (S12XSPIMV1) 2.3.57 Port H Interrupt Flag Register (PIFH) Access: User read/write1 Address 0x0267 7 6 5 4 3 2 1 0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 0 0 0 0 0 0 0 0 R W Reset Figure 2-55. Port H Interrupt Flag Register (PIFH) 1 Read: Anytime Write: Anytime Table 2-54. PIFH Register Field Descriptions Field Description 7-0 PIFH Port H interrupt flag— The flag bit is set after an active edge was applied to the associated input pin.
PAGE 113
Port Integration Module (S12XSPIMV1) 2.3.59 Port J Input Register (PTIJ) Access: User read1 Address 0x0269 R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0 u u u u u u u u W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-57. Port J Input Register (PTIJ) 1 Read: Anytime Write:Never, writes to this register have no effect Table 2-56.
PAGE 114
Port Integration Module (S12XSPIMV1) 2.3.61 Port J Reduced Drive Register (RDRJ) Access: User read/write1 Address 0x026B 7 6 RDRJ7 RDRJ6 0 0 R 5 4 3 2 0 0 0 0 1 0 RDRJ1 RDRJ0 0 0 W Reset 0 0 0 0 Figure 2-59. Port J Reduced Drive Register (RDRJ) 1 Read: Anytime Write: Anytime Table 2-58.
PAGE 115
Port Integration Module (S12XSPIMV1) 2.3.63 Port J Polarity Select Register (PPSJ) Access: User read/write1 Address 0x026D 7 6 PPSJ7 PPSJ6 0 0 R 5 4 3 2 0 0 0 0 1 0 PPSJ1 PPSJ0 0 0 W Reset 0 0 0 0 Figure 2-61. Port J Polarity Select Register (PPSJ) 1 Read: Anytime Write: Anytime Table 2-60.
PAGE 116
Port Integration Module (S12XSPIMV1) 2.3.65 Port J Interrupt Flag Register (PIFJ) Access: User read/write1 Address 0x026F 7 6 PIFJ7 PIFJ6 0 0 R 5 4 3 2 0 0 0 0 1 0 PIFJ1 PIFJ0 0 0 W Reset 0 0 0 0 Figure 2-63. Port J Interrupt Flag Register (PIFJ) 1 Read: Anytime Write: Anytime Table 2-62. PIFJ Register Field Descriptions Field Description 7-6, 1-0 PIFJ Port J interrupt flag— The flag bit is set after an active edge was applied to the associated input pin.
PAGE 117
Port Integration Module (S12XSPIMV1) 2.3.67 Port AD0 Data Register 1 (PT1AD0) Access: User read/write1 Address 0x0271 7 6 5 4 3 2 1 0 PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-65. Port AD0 Data Register 1 (PT1AD0) 1 Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-64.
PAGE 118
Port Integration Module (S12XSPIMV1) 2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0) Access: User read/write1 Address 0x0273 7 6 5 4 3 2 1 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 2-67. Port AD0 Data Direction Register 1 (DDR1AD0) 1 Read: Anytime Write: Anytime Table 2-66.
PAGE 119
Port Integration Module (S12XSPIMV1) 2.3.71 Port AD0 Reduced Drive Register 1 (RDR1AD0) Access: User read/write1 Address 0x0275 7 6 5 4 3 2 1 0 RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 2-69. Port AD0 Reduced Drive Register 1 (RDR1AD0) 1 Read: Anytime Write: Anytime Table 2-68.
PAGE 120
Port Integration Module (S12XSPIMV1) 2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0) Access: User read/write1 Address 0x0277 7 6 5 4 3 2 1 0 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 2-71. Port AD0 Pull Up Enable Register 1 (PER1AD0) 1 Read: Anytime Write: Anytime Table 2-70.
PAGE 121
Port Integration Module (S12XSPIMV1) 2.4.2 Registers A set of configuration registers is common to all ports with exception of the ATD port (Table 2-71). All registers can be written at any time, however a specific configuration might not become active. For example selecting a pull-up device: This device does not become active while the port is used as a push-pull output. Table 2-71.
PAGE 122
Port Integration Module (S12XSPIMV1) NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. PTI 0 1 PT 0 PIN 1 DDR 0 1 data out Module output enable module enable Figure 2-73. Illustration of I/O pin functionality 2.4.2.
PAGE 123
Port Integration Module (S12XSPIMV1) 2.4.2.7 Wired-or mode register (WOMx) If the pin is used as an output this register turns off the active high drive. This allows wired-or type connections of outputs. 2.4.2.8 Interrupt enable register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 2.4.2.
PAGE 124
Port Integration Module (S12XSPIMV1) Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (2.3.14/2-83) and clearing the I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input.
PAGE 125
Port Integration Module (S12XSPIMV1) Port P pins PP[7:3] can be used for either general purpose I/O with pin interrupt capability, or with the PWM or with the channels of the standard Timer.subsystem. Port P pins PP[2,0] can be used for either general purpose I/O, or with the PWM or with the TIM or with the SCI1 subsystem. Port P pin PP[1] can be used for either general purpose I/O, or with the PWM or with the TIM subsystem. 2.4.3.
PAGE 126
Port Integration Module (S12XSPIMV1) Table 2-72. Pulse Detection Criteria Mode Pulse STOP1 STOP Unit Ignored Uncertain Valid tpulse ≤ 3 bus clocks tpulse ≤ tpign 3 < tpulse < 4 bus clocks tpign < tpulse < tpval tpulse ≥ 4 bus clocks tpulse ≥ tpval 1 These values include the spread of the oscillator frequency over temperature, voltage and process. tpulse Figure 2-75.
PAGE 127
Chapter 3 Memory Mapping Control (S12XMMCV4) Revision History Rev. No. (Item No.) Date (Submitted By) v04.09 01-Feb-08 - Minor changes v04.10 17-Feb-09 - Minor changes v04.11 30-Jun-10 3.1 Sections Affected 3.3.2.7/3-139 Substantial Change(s) - Removed confusing statements in EPAGE description Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is shown in Figure 3-1.
PAGE 128
Memory Mapping Control (S12XMMCV4) 3.1.1 Terminology Table 3-1.
PAGE 129
Memory Mapping Control (S12XMMCV4) 3.1.3 S12X Memory Mapping The S12X architecture implements a number of memory mapping schemes including • a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit address load/store instructions. • a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit address load/store instructions.
PAGE 130
Memory Mapping Control (S12XMMCV4) CPU BDM MMC Address Decoder & Priority DBG Target Bus Controller Data FLASH PGMFLASH RAM Peripherals Figure 3-1. MMC Block Diagram 3.2 External Signal Description The user is advised to refer to the SoC Guide for port configuration and location of external bus signals. Some pins may not be bonded out in all implementations. Table 3-2 outlines the pin names and functions. It also provides a brief description of their operation. Table 3-2.
PAGE 131
Memory Mapping Control (S12XMMCV4) 3.3 3.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
PAGE 132
Memory Mapping Control (S12XMMCV4) 3.3.2.1 Mode Register (MODE) Address: 0x000B PRR 7 R W Reset MODC MODC1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 3-2). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE) Read: Anytime. Write: Only if a transition is allowed (see Figure 3-5). The MODE bits of the MODE register are used to establish the MCU operating mode. Table 3-3.
PAGE 133
Memory Mapping Control (S12XMMCV4) 3.3.2.2 Global Page Index Register (GPAGE) Address: 0x0010 7 R 0 W Reset 0 6 5 4 3 2 1 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 3-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used to construct a 23 bit address in the global map format.
PAGE 134
Memory Mapping Control (S12XMMCV4) 3.3.2.3 Direct Page Register (DIRECT) Address: 0x0011 R W 7 6 5 4 3 2 1 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 Reset Figure 3-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the 256B direct page within the memory map.It is valid for both global and local mapping scheme. Table 3-5.
PAGE 135
Memory Mapping Control (S12XMMCV4) 3.3.2.4 MMC Control Register (MMCCTL1) Address: 0x0013 PRR 7 R W 6 MGRAMON Reset 5 0 0 4 DFIFRON PGMIFRON 0 0 0 3 2 1 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 3-10. MMC Control Register (MMCCTL1) Read: Anytime. . Write: Refer to each bit description. Table 3-6.
PAGE 136
Memory Mapping Control (S12XMMCV4) Write: Anytime These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12). This supports accessing up to 4MB of Flash (in the Global map) within the 64KB Local map. The PPAGE register is effectively used to construct paged Flash addresses in the Local map format.
PAGE 137
Memory Mapping Control (S12XMMCV4) Read: Anytime Write: Anytime These eight index bits are used to page 4KB blocks into the RAM page window located in the local (CPU or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 3-14). This supports accessing up to 1022KB of RAM (in the Global map) within the 64KB Local map. The RAM page index register is effectively used to construct paged RAM addresses in the Local map format.
PAGE 138
Memory Mapping Control (S12XMMCV4) The two fixed 4KB pages (0xFE, 0xFF) contain unimplemented area in the range not occupied by RAM if RAMSIZE is less than 8KB (Refer to Section 3.4.2.3, “Implemented Memory Map). S12XS Family Reference Manual, Rev. 1.
PAGE 139
Memory Mapping Control (S12XMMCV4) 3.3.2.7 Data FLASH Page Index Register (EPAGE) Address: 0x0017 R W 7 6 5 4 3 2 1 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 1 1 1 1 1 1 1 0 Reset Figure 3-15. Data FLASH Page Index Register (EPAGE) Read: Anytime Write: Anytime These eight index bits are used to page 1KB blocks into the Data FLASH page window located in the local (CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 3-16).
PAGE 140
Memory Mapping Control (S12XMMCV4) 3.4 Functional Description The MMC block performs several basic functions of the S12X sub-system operation: MCU operation modes, priority control, address mapping, select signal generation and access limitations for the system. Each aspect is described in the following subsections. 3.4.1 • • MCU Operating Mode Normal single-chip mode There is no external bus in this mode. The MCU program is executed from the internal memory and no external accesses are allowed.
PAGE 141
Memory Mapping Control (S12XMMCV4) CPU and BDM Local Memory Map Global Memory Map 0x00_0000 2KB REGISTERS 0x00_0800 2KB RAM RAM 253*4KB paged 0x0800 0x0C00 0x1000 0x0F_E000 2KB REGISTERS 1KB Data Flash window 8KB RAM EPAGE 0x10_0000 Reserved 4KB RAM window Data FLASH 256*1KB paged RPAGE 0x2000 256KB 0x0000 1M minus 2KB 0x00_1000 8KB RAM 0x4000 0x13_FC00 Unimplemented Space 0x8000 16KB FLASH window 2.
PAGE 142
Memory Mapping Control (S12XMMCV4) 3.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index register in MMC allows accessing up to 4MB of FLASH or ROM in the global memory map by using the eight page index bits to page 256 16KB blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. The page value for the program page window is stored in the PPAGE register.
PAGE 143
Memory Mapping Control (S12XMMCV4) Expansion of the BDM Local Address Map PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. 3.4.2.
PAGE 144
Memory Mapping Control (S12XMMCV4) BDM HARDWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 BDMGPR Register [6:0] Bit0 BDM Local Address BDM FIRMWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 BDMGPR Register [6:0] Bit0 CPU Local Address Figure 3-18. BDMGPR Address Mapping 3.4.2.3 Implemented Memory Map The global memory spaces reserved for the internal resources (RAM, Data FLASH, and FLASH) are not determined by the MMC module.
PAGE 145
Memory Mapping Control (S12XMMCV4) In single-chip modes accesses by the CPU (except for firmware commands) to any of the unimplemented areas (see Figure 3-19) will result in an illegal access reset (system reset) in case of no MPU error. BDM accesses to the unimplemented areas are allowed but the data will be undefined.No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block Guide).
PAGE 146
Memory Mapping Control (S12XMMCV4) CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS Unimplemented RAM 0x0000 0x0800 0x0C00 0x1000 RAM 2K REGISTERS 1K Data Flash window EPAGE 0x0F_FFFF Data FLASH Reserved DF_HIGH 4K RAM window RPAGE 0x2000 Data FLASH Resources 8K RAM DFLASHSIZE RAMSIZE RAM_LOW 0x4000 0x13_FFFF Unpaged 16K FLASH Unimplemented Space 0x8000 16K FLASH window PPAGE 0x3F_FFFF 0xC000 Unimplemented FLASH Unpaged 16K FLASH Reset Vectors FLASH_LOW
PAGE 147
Memory Mapping Control (S12XMMCV4) 3.4.3 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM ) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal resources are connected to specific target buses (see Figure 3-20). CPU BDM S12X1 S12X0 MMC Address Decoder & Priority DBG Target Bus Controller XBUS0 Data FLASH PGMFLASH RAM Peripherals Figure 3-20.
PAGE 148
Memory Mapping Control (S12XMMCV4) 3.4.3.1 Master Bus Prioritization regarding access conflicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing accesses from different masters to the same target bus: • CPU always has priority over BDM . • BDM has priority over CPU when its access is stalled for more than 128 cycles.
PAGE 149
Memory Mapping Control (S12XMMCV4) During the execution of an RTC instruction the CPU performs the following steps: 1. Pulls the previously stored PPAGE value from the stack 2. Pulls the 16-bit return address from the stack and loads it into the PC 3. Writes the PPAGE value into the PPAGE register 4. Refills the queue and resumes execution at the return address This sequence is uninterruptible. The RTC can be executed from anywhere in the local CPU memory space.
PAGE 150
Memory Mapping Control (S12XMMCV4) S12XS Family Reference Manual, Rev. 1.
PAGE 151
Chapter 4 Interrupt (S12XINTV2) Table 4-1. Revision History Revision Number Revision Date Sections Affected V02.00 01 Jul 2005 4.1.2/4-152 V02.04 11 Jan 2007 4.3.2.2/4-157 4.3.2.4/4-158 V02.05 20 Mar 2007 4.4.6/4-164 V02.07 13 Dec 2011 4.5.3.1/4-166 4.1 Description of Changes Initial V2 release, added new features: - XGATE threads can be interrupted. - SYS instruction vector. - Access violation interrupt vectors. - Added Notes for devices without XGATE module.
PAGE 152
Interrupt (S12XINTV2) 4.1.1 Glossary The following terms and abbreviations are used in the document. Table 4-2. Terminology Term CCR Condition Code Register (in the S12X CPU) DMA Direct Memory Access INT Interrupt IPL Interrupt Processing Level ISR Interrupt Service Routine MCU XGATE IRQ XIRQ 4.1.
PAGE 153
Interrupt (S12XINTV2) 4.1.3 • • • • Modes of Operation Run mode This is the basic mode of operation. Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode In stop mode, the XINT module is frozen.
PAGE 154
Interrupt (S12XINTV2) 4.1.4 Block Diagram Figure 4-1 shows a block diagram of the XINT module.
PAGE 155
Interrupt (S12XINTV2) 4.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XINT module. 4.3.1 Module Memory Map Table 4-3 gives an overview over all XINT module registers. Table 4-3.
PAGE 156
Interrupt (S12XINTV2) 4.3.2 Register Descriptions This section describes in address order all the XINT module registers and their individual bits.
PAGE 157
Interrupt (S12XINTV2) 4.3.2.1 Interrupt Vector Base Register (IVBR) Address: 0x0121 7 6 5 R 3 2 1 0 1 1 1 IVB_ADDR[7:0] W Reset 4 1 1 1 1 1 Figure 4-3. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Table 4-4. IVBR Field Descriptions Field Description 7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e.
PAGE 158
Interrupt (S12XINTV2) Table 4-6. XGATE Interrupt Priority Levels Priority low high 4.3.2.
PAGE 159
Interrupt (S12XINTV2) Address: 0x0128 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 4-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x0129 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 4-7.
PAGE 160
Interrupt (S12XINTV2) Address: 0x012C 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 4-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x012D 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 4-11.
PAGE 161
Interrupt (S12XINTV2) Table 4-8. INT_CFDATA0–7 Field Descriptions Field Description 7 RQST XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the configuration register for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit.
PAGE 162
Interrupt (S12XINTV2) 4.4.1 S12X Exception Requests The CPU handles both reset requests and interrupt requests. The XINT module contains registers to configure the priority level of each I bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the priority of a pending interrupt request. 4.4.
PAGE 163
Interrupt (S12XINTV2) 4.4.3 XGATE Requests If the XGATE module is implemented on the device, the XINT module is also used to process all exception requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed in the subsections below. 4.4.3.1 XGATE Request Prioritization An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the associated configuration register is set to 1 (please refer to Section 4.3.2.
PAGE 164
Interrupt (S12XINTV2) NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)). 4.4.5 Reset Exception Requests The XINT module supports three system reset exception request types (for details please refer to the Clock and Reset Generator module (CRG)): 1.
PAGE 165
Interrupt (S12XINTV2) 4.5 4.5.1 Initialization/Application Information Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module).
PAGE 166
Interrupt (S12XINTV2) 0 Stacked IPL IPL in CCR 0 0 4 0 0 0 4 7 4 3 1 0 7 6 RTI L7 5 4 RTI Processing Levels 3 L3 (Pending) 2 L4 RTI 1 L1 (Pending) 0 RTI Reset Figure 4-14. Interrupt Processing Example 4.5.3 4.5.3.1 Wake Up from Stop or Wait Mode CPU Wake Up from Stop or Wait Mode Only I bit maskable interrupt requests which are configured to be handled by the CPU are capable of waking the MCU from wait mode.
PAGE 167
Interrupt (S12XINTV2) 4.5.3.2 XGATE Wake Up from Stop or Wait Mode Interrupt request channels which are configured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU. S12XS Family Reference Manual, Rev. 1.
PAGE 168
Interrupt (S12XINTV2) S12XS Family Reference Manual, Rev. 1.
PAGE 169
Chapter 5 Background Debug Module (S12XBDMV2) Table 5-1. Revision History Revision Number Revision Date V02.00 07 Mar 2006 - First version of S12XBDMV2 V02.01 14 May 2008 - Introduced standardized Revision History Table V02.02 12 Sep 2012 - Minor formatting corrections 5.1 Sections Affected Description of Changes Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12X core platform.
PAGE 170
Background Debug Module (S12XBDMV2) • • • • • • • • • • • • • Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single chip mode Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 14 firmware commands execute from the standard BDM firmware lookup table Software control of BDM operation during wait mode Software selectable clocks Global page access functionality Enab
PAGE 171
Background Debug Module (S12XBDMV2) 5.1.2.3 Low-Power Modes The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM firmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available.
PAGE 172
Background Debug Module (S12XBDMV2) 5.3 Memory Map and Register Definition 5.3.1 Module Memory Map Table 5-2 shows the BDM memory map when BDM is active. Table 5-2. BDM Memory Map 5.3.2 Global Address Module Size (Bytes) 0x7FFF00–0x7FFF0B BDM registers 12 0x7FFF0C–0x7FFF0E BDM firmware ROM 3 0x7FFF0F Family ID (part of BDM firmware ROM) 1 0x7FFF10–0x7FFFFF BDM firmware ROM 240 Register Descriptions A summary of the registers associated with the BDM is shown in Figure 5-2.
PAGE 173
Background Debug Module (S12XBDMV2) Global Address Register Name 0x7FFF07 Bit 7 6 5 4 3 0 0 0 0 0 BGAE BGP6 BGP5 BGP4 0 0 0 0 0 0 0 BDMCCRH R 2 1 Bit 0 CCR10 CCR9 CCR8 BGP3 BGP2 BGP1 BGP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x7FFF08 BDMGPR R W 0x7FFF09 Reserved R W 0x7FFF0A Reserved R W 0x7FFF0B Reserved R W = Unimplemented, Reserved = Indeterminate X = Implemented (do not alter) = Always read zero 0 Figure 5-2.
PAGE 174
Background Debug Module (S12XBDMV2) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, but subject to the following: — ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single chip and emulation modes). — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode.
PAGE 175
Background Debug Module (S12XBDMV2) Table 5-3. BDMSTS Field Descriptions (continued) Field Description 2 CLKSW Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send.
PAGE 176
Background Debug Module (S12XBDMV2) 5.3.2.2 BDM CCR LOW Holding Register (BDMCCRL) Register Global Address 0x7FFF06 7 6 5 4 3 2 1 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 Special Single-Chip Mode 1 1 0 0 1 0 0 0 All Other Modes 0 0 0 0 0 0 0 0 R W Reset Figure 5-4.
PAGE 177
Background Debug Module (S12XBDMV2) 5.3.2.4 BDM Global Page Index Register (BDMGPR) Register Global Address 0x7FFF08 R W Reset 7 6 5 4 3 2 1 0 BGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0 0 0 0 0 0 0 0 0 Figure 5-6. BDM Global Page Register (BDMGPR) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured Table 5-5.
PAGE 178
Background Debug Module (S12XBDMV2) 5.4.1 Security If the user resets into special single chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip non-volatile memory (e.g. EEPROM and Flash EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set.
PAGE 179
Background Debug Module (S12XBDMV2) 5.4.3 BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU on the SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control registers, and all external memory.
PAGE 180
Background Debug Module (S12XBDMV2) Table 5-6. Hardware Commands (continued) Command WRITE_WORD Opcode (hex) C8 Data Description 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Must be aligned access. NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 5.4.
PAGE 181
Background Debug Module (S12XBDMV2) Table 5-7. Firmware Commands Command1 Opcode (hex) Data Description READ_NEXT2 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. READ_SP 67 16-bit data out Read stack pointer.
PAGE 182
Background Debug Module (S12XBDMV2) 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For devices with external bus: The following cycle count information is only valid when the external wait function is not used (see wait bit of EBI sub-block). During an external wait the BDM can not steal a cycle.
PAGE 183
Background Debug Module (S12XBDMV2) Hardware Read 8 Bits AT ~16 TC/Bit 16 Bits AT ~16 TC/Bit Command Address 150-BC Delay 16 Bits AT ~16 TC/Bit Data Next Command 150-BC Delay Hardware Write Command Address Data Next Command 48-BC DELAY Firmware Read Command Next Command Data 36-BC DELAY Firmware Write Command Data Next Command 76-BC Delay GO, TRACE Command Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Figure 5-7. BDM Command Structure 5.4.
PAGE 184
Background Debug Module (S12XBDMV2) cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 5-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system.
PAGE 185
Background Debug Module (S12XBDMV2) BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse High-Impedance High-Impedance High-Impedance Perceived Start of Bit Time R-C Rise BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1) S12XS Family Reference Manual Rev. 1.
PAGE 186
Background Debug Module (S12XBDMV2) Figure 5-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge.
PAGE 187
Background Debug Module (S12XBDMV2) compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. BDM Clock (Target MCU) 16 Cycles Target Transmits ACK Pulse High-Impedance High-Impedance 32 Cycles Speedup Pulse Minimum Delay From the BDM Command BKGD Pin Earliest Start of Next Bit 16th Tick of the Last Command Bit Figure 5-11.
PAGE 188
Background Debug Module (S12XBDMV2) Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 5-11 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
PAGE 189
Background Debug Module (S12XBDMV2) GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin.
PAGE 190
Background Debug Module (S12XBDMV2) Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening.
PAGE 191
Background Debug Module (S12XBDMV2) The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued.
PAGE 192
Background Debug Module (S12XBDMV2) within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication.
PAGE 193
Background Debug Module (S12XBDMV2) after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. 5.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse.
PAGE 194
Background Debug Module (S12XBDMV2) S12XS Family Reference Manual, Rev. 1.
PAGE 195
Chapter 6 S12X Debug (S12XDBGV3) Module Table 6-1. Revision History Revision Number Revision Date Sections Affected V03.20 14 Sep 2007 6.3.2.7/6-205 - Clarified reserved State Sequencer encodings. V03.21 23 Oct 2007 6.4.2.2/6-218 6.4.2.4/6-219 - Added single databyte comparison limitation information - Added statement about interrupt vector fetches whilst tagging. V03.22 12 Nov 2007 6.4.5.2/6-223 6.4.5.5/6-227 - Removed LOOP1 tracing restriction NOTE. - Added pin reset effect NOTE. V03.
PAGE 196
S12X Debug (S12XDBGV3) Module Table 6-2. Glossary Of Terms (continued) Term Definition Data Line 64-bit data entity CPU CPU12X module Tag Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 6.1.2 Overview The comparators monitor the bus activity of the CPU12X. When a match occurs the control logic can trigger the state sequencer to a new state.
PAGE 197
S12X Debug (S12XDBGV3) Module — Normal: change of flow (COF) PC information is stored (see Section 6.4.5.2.1) for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Pure PC: All program counter addresses are stored.
PAGE 198
S12X Debug (S12XDBGV3) Module 6.1.5 Block Diagram TAGS TAGHITS BREAKPOINT REQUESTS S12XCPU SECURE COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL COMPARATOR A BUS INTERFACE S12XCPU BUS TAG & TRIGGER CONTROL LOGIC MATCH1 TRIGGER STATE STATE SEQUENCER STATE MATCH2 MATCH3 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 6-1. Debug Module Block Diagram 6.2 External Signal Description The S12XDBG sub-module features no external signals. 6.
PAGE 199
S12X Debug (S12XDBGV3) Module Address Name Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SC3 SC2 SC1 SC0 0x0024 DBGTBH R W 0x0025 DBGTBL R W Bit 7 0x0026 DBGCNT R W 0 0x0027 DBGSCRX 0 0 0 0 0x0027 DBGMFR R W R W 0 0 0 0 MC3 MC2 MC1 MC0 NDB TAG BRK RW RWE reserved COMPE SZ TAG BRK RW RWE reserved COMPE Bit 22 21 20 19 18 17 Bit 16 0x00281 0x00282 DBGXCTL R (COMPA/C
PAGE 200
S12X Debug (S12XDBGV3) Module 6.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0020 7 R W Reset 6 ARM 0 0 TRIG 0 5 4 3 2 reserved BDM DBGBRK reserved 0 0 0 0 1 0 COMRV 0 0 Figure 6-3. Debug Control Register (DBGC1) Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 5:2 anytime S12XDBG is not armed.
PAGE 201
S12X Debug (S12XDBGV3) Module Table 6-4. DBGC1 Field Descriptions (continued) Field Description 3 DBGBRK S12XDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint to S12XCPU upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please refer to Section 6.4.7 for further details. 0 No breakpoint on trigger.
PAGE 202
S12X Debug (S12XDBGV3) Module Table 6-7. SSF[2:0] — State Sequence Flag Bit Encoding 6.3.2.3 SSF[2:0] Current State 000 State0 (disarmed) 001 State1 010 State2 011 State3 100 Final State 101,110,111 Reserved Debug Trace Control Register (DBGTCR) Address: 0x0022 R W Reset 7 6 reserved TSOURCE 0 0 5 4 3 TRANGE 0 2 1 TRCMOD 0 0 0 TALIGN 0 0 0 Figure 6-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
PAGE 203
S12X Debug (S12XDBGV3) Module Table 6-9. TRANGE Trace Range Encoding TRANGE Tracing Range 00 Trace from all addresses (No filter) 01 Trace only in address range from $00000 to Comparator D 10 Trace only in address range from Comparator C to $7FFFFF 11 Trace only in range from Comparator C to Comparator D Table 6-10. TRCMOD Trace Mode Bit Encoding TRCMOD Description 00 Normal 01 Loop1 10 Detail 11 Pure PC Table 6-11. TALIGN Trace Alignment Encoding 6.3.2.
PAGE 204
S12X Debug (S12XDBGV3) Module Table 6-13. CDCM Encoding CDCM Description 00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match. 01 Match2 mapped to comparator C/D inside range....... Match3 disabled. 10 Match2 mapped to comparator C/D outside range....... Match3 disabled. 11 Reserved(1) 1. Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D Table 6-14. ABCM Encoding ABCM Description 00 Match0 mapped to comparator A match.......
PAGE 205
S12X Debug (S12XDBGV3) Module 6.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 7 R 6 5 4 0 3 2 1 0 — 0 — 0 — 0 CNT W Reset POR 0 0 — 0 — 0 — 0 — 0 = Unimplemented or Reserved Figure 6-8. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 6-16. DBGCNT Field Descriptions Field Description 6–0 CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
PAGE 206
S12X Debug (S12XDBGV3) Module next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 6-18. State Control Register Access Encoding 6.3.2.7.
PAGE 207
S12X Debug (S12XDBGV3) Module Table 6-20. State1 Sequencer Next State Selection (continued) SC[3:0] 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State2....... Match3 triggers to State3......
PAGE 208
S12X Debug (S12XDBGV3) Module Table 6-22. State2 —Sequencer Next State Selection (continued) SC[3:0] 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Match3 triggers to Final State....... Other matches have no effect Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State1....... Match2 triggers to State3.......
PAGE 209
S12X Debug (S12XDBGV3) Module Table 6-24. State3 — Sequencer Next State Selection SC[3:0] 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to Final State Match0 triggers to State1....... Other matches have no effect Match0 triggers to State2....... Other matches have no effect Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect Match1 triggers to State1.......
PAGE 210
S12X Debug (S12XDBGV3) Module Comparators B and D consist of four register bytes (three address bus compare registers and a control register). Each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the COMRV bits in the DBGC1 register.
PAGE 211
S12X Debug (S12XDBGV3) Module unimplemented bus, thus preventing proper operation. The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 6-26. Table 6-26.
PAGE 212
S12X Debug (S12XDBGV3) Module Table 6-27. DBGXCTL Field Descriptions (continued) Field Description 0 COMPE Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled for state sequence triggers or tag generation Table 6-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue.
PAGE 213
S12X Debug (S12XDBGV3) Module 6.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 6-16. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 6-26 for visible register encoding. Write: If DBG not armed. See Table 6-26 for visible register encoding. Table 6-30.
PAGE 214
S12X Debug (S12XDBGV3) Module 6.3.2.8.5 Debug Comparator Data High Register (DBGXDH) Address: 0x002C R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 6-18. Debug Comparator Data High Register (DBGXDH) Read: Anytime. See Table 6-26 for visible register encoding. Write: If DBG not armed. See Table 6-26 for visible register encoding. Table 6-32.
PAGE 215
S12X Debug (S12XDBGV3) Module 6.3.2.8.7 Debug Comparator Data High Mask Register (DBGXDHM) Address: 0x002E R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 6-20. Debug Comparator Data High Mask Register (DBGXDHM) Read: Anytime. See Table 6-26 for visible register encoding. Write: If DBG not armed. See Table 6-26 for visible register encoding. Table 6-34.
PAGE 216
S12X Debug (S12XDBGV3) Module 6.4.1 S12XDBG Operation Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the CPU12X . The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU12X . Comparators can be configured to monitor address and databus.
PAGE 217
S12X Debug (S12XDBGV3) Module when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1).
PAGE 218
S12X Debug (S12XDBGV3) Module NOTE Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.
PAGE 219
S12X Debug (S12XDBGV3) Module Table 6-38. NDB and MASK bit dependency 6.4.2.4 NDB DBGxDHM[n] / DBGxDLM[n] Comment 0 0 Do not compare data bus bit. 0 1 Compare data bus bit. Match on equivalence. 1 0 Do not compare data bus bit. 1 1 Compare data bus bit. Match on difference. Range Comparisons When using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data and data mask registers.
PAGE 220
S12X Debug (S12XDBGV3) Module 6.4.3 Trigger Modes Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in the following sections. 6.4.3.
PAGE 221
S12X Debug (S12XDBGV3) Module Table 6-39. Trigger Priorities Highest Lowest 6.4.
PAGE 222
S12X Debug (S12XDBGV3) Module 6.4.4.1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 6.3.2.3). If TSOURCE in the trace control register DBGTCR is cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request.
PAGE 223
S12X Debug (S12XDBGV3) Module be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.3 Storing with End-Trigger Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the S12XDBG module will become disarmed and no more data will be stored.
PAGE 224
S12X Debug (S12XDBGV3) Module SUB_1 BRN * ADDR1 NOP DBNE A,PART5 IRQ_ISR LDAB STAB RTI #$F0 VAR_C1 ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 ; The execution flow taking into account the IRQ is as follows MARK1 IRQ_ISR SUB_1 ADDR1 6.4.5.2.
PAGE 225
S12X Debug (S12XDBGV3) Module 6.4.5.3 Trace Buffer Organization Referring to Table 6-40. ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode.
PAGE 226
S12X Debug (S12XDBGV3) Module 6.4.5.3.1 Information Byte Organization The format of the control information byte is dependent upon the active trace mode as described below. In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control information. In Detail Mode, CXINF contains the control information. CPU12X Information Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSD CVA 0 CDV 0 0 0 0 Figure 6-23. CPU12X Information Byte CINF Table 6-41.
PAGE 227
S12X Debug (S12XDBGV3) Module Table 6-42. CXINF Field Descriptions (continued) Field 5 CRW 6.4.5.4 Description Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing CPU12X activity in Detail Mode.
PAGE 228
S12X Debug (S12XDBGV3) Module 6.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. Each comparator control register features a TAG bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address.
PAGE 229
S12X Debug (S12XDBGV3) Module Table 6-43.
PAGE 230
S12X Debug (S12XDBGV3) Module Table 6-44. Breakpoint Mapping Summary 1 1 0 X Breakpoint to SWI 1 1 1 0 Breakpoint to BDM 1 1 1 1 No Breakpoint BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set.
PAGE 231
Chapter 7 Security (S12XS9SECV2) Table 7-1. Revision History Version Number Revision Date Effective Date 02.00 27 Aug 2004 08 Sep 2004 reviewed and updated for S12XD architecture 02.01 21 Feb 2007 21 Feb 2007 added S12XE, S12XF and S12XS architectures 02.02 19 Apr 2007 19 Apr 2007 corrected statement about Backdoor key access via BDM on XE, XF, XS 7.
PAGE 232
Security (S12XS9SECV2) Table 7-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode NS SS EEPROM Array Access ✔ NVM Commands BDM NX ES Secure Mode EX ST NS SS ✔ ✔ ✔ ✔1 ✔ ✔1 ✔1 ✔ ✔ — ✔2 NX ES EX ST DBG Module Trace ✔ ✔ — — Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. 1 BDM hardware commands restricted to peripheral registers only. 2 7.1.2 Modes of Operation 7.1.
PAGE 233
Security (S12XS9SECV2) SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. Table 7-4. Security Bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured) NOTE Please refer to the Flash block guide for actual security configuration (in section “Flash Module Security”). 7.1.
PAGE 234
Security (S12XS9SECV2) 7.1.4.1 • • • Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. 7.1.4.2 • • • • Normal Single Chip Mode (NS) Special Single Chip Mode (SS) BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted.
PAGE 235
Security (S12XS9SECV2) 7.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 7.1.5.1 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method.
PAGE 236
Security (S12XS9SECV2) 7.1.7 Complete Memory Erase (Special Modes) The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled.
PAGE 237
Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-1. Revision History Revision Number Revision Date V01.00 26 Oct. 2005 V01.01 02 Nov 2006 8.4.1.1/8-254 Table “Examples of IPLL Divider settings”: corrected $32 to $31 V01.02 4 Mar. 2008 8.4.1.4/8-257 8.4.3.3/8-261 Corrected details V01.03 1 Sep. 2008 Table 8-14 V01.04 20 Nov. 2008 8.3.2.4/8-243 V01.05 19. Sep 2009 8.5.1/8-263 Modified Note below Table 8-17./8-263 V01.06 18. Sep 2012 Table 8-14 8.5.
PAGE 238
S12XE Clocks and Reset Generator (S12XECRGV1) • • 8.1.2 System Reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset Real-Time Interrupt (RTI) Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12XECRG. • Run Mode All functional parts of the S12XECRG are running during normal Run Mode.
PAGE 239
S12XE Clocks and Reset Generator (S12XECRGV1) Illegal Address Reset S12X_MMC Power on Reset Voltage Regulator Low Voltage Reset ICRG RESET CM Fail Clock Monitor OSCCLK EXTAL Oscillator XTAL COP Timeout XCLKS Reset Generator Clock Quality Checker System Reset Bus Clock Core Clock COP RTI Oscillator Clock Registers PLLCLK VDDPLL IPLL VSSPLL Real Time Interrupt Clock and Reset Control PLL Lock Interrupt Self Clock Mode Interrupt Figure 8-1. Block diagram of S12XECRG 8.
PAGE 240
S12XE Clocks and Reset Generator (S12XECRGV1) 8.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12XECRG. 8.3.1 Module Memory Map Figure 8-2 gives an overview on all S12XECRG registers.
PAGE 241
S12XE Clocks and Reset Generator (S12XECRGV1) 8.3.2 Register Descriptions This section describes in address order all the S12XECRG registers and their individual bits. 8.3.2.1 S12XECRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range. Module Base + 0x0000 7 6 5 4 3 2 1 0 0 0 0 R VCOFRQ[1:0] SYNDIV[5:0] W Reset 0 0 0 0 0 Figure 8-3.
PAGE 242
S12XE Clocks and Reset Generator (S12XECRGV1) 8.3.2.2 S12XECRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the IPLL multiplier steps. Module Base + 0x0001 7 6 5 4 3 2 1 0 0 0 0 R REFFRQ[1:0] REFDIV[5:0] W Reset 0 0 0 0 0 Figure 8-4. S12XECRG Reference Divider Register (REFDV) Read: Anytime Write: Anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit.
PAGE 243
S12XE Clocks and Reset Generator (S12XECRGV1) Module Base + 0x0002 R 7 6 5 0 0 0 4 3 2 1 0 0 0 2 1 0 ILAF SCMIF 0 0 POSTDIV[4:0] W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-5. S12XECRG Post Divider Register (POSTDIV) Read: Anytime Write: Anytime except if PLLSEL = 1 f VCO f PLL = -------------------------------------( 2xPOSTDIV ) NOTE If POSTDIV = $00 then fPLL is identical to fVCO (divide by one). 8.3.2.
PAGE 244
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-4. CRGFLG Field Descriptions Field Description 7 RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. 6 PORF Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1.
PAGE 245
S12XE Clocks and Reset Generator (S12XECRGV1) Read: Anytime Write: Anytime Table 8-5. CRGINT Field Descriptions Field 7 RTIE Description Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. 4 LOCKIE Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 SCMIE Self Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled.
PAGE 246
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-6. CLKSEL Field Descriptions Field 7 PLLSEL 6 PSTP Description PLL Select Bit Write: Anytime. Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
PAGE 247
S12XE Clocks and Reset Generator (S12XECRGV1) Read: Anytime Write: Refer to each bit for individual write conditions Table 8-7. PLLCTL Field Descriptions Field Description 7 CME Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock Mode. Note: Operating with CME=0 will not detect any loss of clock.
PAGE 248
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-8. FM Amplitude selection FM1 8.3.2.8 FM Amplitude / fVCO Variation FM0 0 0 FM off 0 1 ±1% 1 0 ±2% 1 1 ±4% S12XECRG RTI Control Register (RTICTL) This register selects the timeout period for the Real Time Interrupt. Module Base + 0x0007 7 6 5 4 3 2 1 0 RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 0 0 0 0 0 0 0 0 R W Reset Figure 8-10.
PAGE 249
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-10.
PAGE 250
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-11. RTI Frequency Divide Rates for RTDEC=1 RTR[6:4] = RTR[3:0] 000 (1x103) 001 (2x103) 010 (5x103) 011 (10x103) 100 (20x103) 101 (50x103) 110 (100x103) 111 (200x103) 0110 (÷7) 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1.4x106 0111 (÷8) 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1.6x106 1000 (÷9) 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1.
PAGE 251
S12XE Clocks and Reset Generator (S12XECRGV1) The COP time-out period is restarted if one these two conditions is true: 1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. or 2. Changing RSBCK bit from “0” to “1”. Table 8-12. COPCTL Field Descriptions Field Description 7 WCOP Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period.
PAGE 252
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-13. COP Watchdog Rates(1) CR2 CR1 OSCCLK Cycles to Timeout CR0 1 1 1 2 24 1. OSCCLK cycles are referenced from the previous COP time-out reset (writing $55/$AA to the ARMCOP register) 8.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the S12XECRG’s functionality.
PAGE 253
S12XE Clocks and Reset Generator (S12XECRGV1) Write: Only in special modes 8.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 8-14.
PAGE 254
S12XE Clocks and Reset Generator (S12XECRGV1) 8.4 Functional Description 8.4.1 Functional Blocks 8.4.1.1 Phase Locked Loop with Internal Filter (IPLL) The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 8-15 shows a block diagram of the IPLL.
PAGE 255
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-14. Examples of IPLL Divider Settings(1) fOSC REFDIV[5:0] fREF 4MHz $01 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz 8MHz $03 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz 4MHz $00 4MHz 01 $09 80MHz 01 $00 80MHz 40MHz 8MHz $00 8MHz 10 $04 80MHz 01 $00 80MHz 40MHz 4MHz $00 4MHz 01 $03 32MHz 00 $01 16MHz 8MHz 4MHz $01 2MHz 01 $18 100MHz 11 $01 1.
PAGE 256
S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.1.2 System Clocks Generator PLLSEL or SCM PLLCLK PHASE LOCK LOOP (IIPLL) STOP 1 SYSCLK ÷2 SCM EXTAL 1 OSCILLATOR Core Clock 0 WAIT(RTIWAI), STOP(PSTP, PRE), RTI ENABLE CLOCK PHASE GENERATOR Bus Clock RTI OSCCLK 0 WAIT(COPWAI), STOP(PSTP, PCE), COP ENABLE XTAL COP Clock Monitor STOP Oscillator Clock Gating Condition = Clock Gate Figure 8-16.
PAGE 257
S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.1.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit.
PAGE 258
S12XE Clocks and Reset Generator (S12XECRGV1) The Sequence for clock quality check is shown in Figure 8-18. CM FAIL CLOCK OK NO EXIT FULL STOP POR LVR SCME=1 & FSTWKP=1 ? NO YES NUM = 0 FSTWKP = 0 ? ENTER SCM YES CLOCK MONITOR RESET ENTER SCM NUM = 50 YES CHECK WINDOW SCM ACTIVE? NUM = NUM-1 YES OSC OK ? NUM = 0 NO NO NUM > 0 ? YES NO SCME = 1 ? NO YES SCM ACTIVE? YES SWITCH TO OSCCLK NO EXIT SCM Figure 8-18.
PAGE 259
S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.1.5 Computer Operating Properly Watchdog (COP) The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 8.4.1.
PAGE 260
S12XE Clocks and Reset Generator (S12XECRGV1) NOTE In order to detect a potential clock loss the CME bit should always be enabled (CME = 1). If CME bit is disabled and the MCU is configured to run on PLLCLK, a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards lower frequencies. As soon as the external clock is available again the system clock ramps up to its IPLL target frequency.
PAGE 261
S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.3.3 Stop Mode All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or COP continues to run in Pseudo Stop Mode. In addition to disabling system and core clocks the S12XECRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual power saving modes (if available).
PAGE 262
S12XE Clocks and Reset Generator (S12XECRGV1) CPU resumes program execution immediately Instruction STOP STOP FSTWKP=1 SCME=1 STOP Interrupt IRQ service IRQ service IRQ service Interrupt Interrupt Power Saving Oscillator Clock Oscillator Disabled PLL Clock Core Clock Self-Clock Mode Figure 8-19. Fast Wake-up from Full Stop Mode: Example 1 .
PAGE 263
S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-16. Reset Summary 8.5.1 Reset Source Local Enable COP Watchdog Reset COPCTL (CR[2:0] nonzero) Description of Reset Operation The reset sequence is initiated by any of the following events: • Low level is detected at the RESET pin (External Reset). • Power on is detected. • Low voltage is detected. • Illegal Address Reset is detected (refer to device MMC information for details). • COP watchdog times out.
PAGE 264
S12XE Clocks and Reset Generator (S12XECRGV1) The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (External Reset), the internal reset remains asserted longer. Figure 8-21. RESET Timing RESET )( )( ICRG drives RESET pin low ) ) SYSCLK possibly SYSCLK not running ) ( ( 128+n cycles 8.5.1.
PAGE 265
S12XE Clocks and Reset Generator (S12XECRGV1) S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50 check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts using Self-Clock Mode. Figure 8-22 and Figure 8-23 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low.
PAGE 266
S12XE Clocks and Reset Generator (S12XECRGV1) 8.6.1 8.6.1.1 Description of Interrupt Operation Real Time Interrupt The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1.
PAGE 267
Chapter 9 Pierce Oscillator (S12XOSCLCPV2) Table 9-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V01.05 19 Jul 2006 - All xclks info was removed V02.00 04 Aug 2006 - Incremented revision to match the design system spec revision 9.1 Introduction The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (1.
PAGE 268
Pierce Oscillator (S12XOSCLCPV2) 9.1.3 Block Diagram Figure 9-1 shows a block diagram of the XOSC. Monitor_Failure Clock Monitor OSCCLK Peak Detector Gain Control VDDPLL = 1.8 V Rf XTAL EXTAL Figure 9-1. XOSC Block Diagram 9.2 External Signal Description This section lists and describes the signals that connect off chip 9.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry.
PAGE 269
Pierce Oscillator (S12XOSCLCPV2) from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 9-2.
PAGE 270
Pierce Oscillator (S12XOSCLCPV2) 9.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the oscillator module. 9.4 Functional Description The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. The oscillator block has two external pins, EXTAL and XTAL.
PAGE 271
Chapter 10 Analog-to-Digital Converter (ADC12B16CV1) Table 10-1. Revision History Revision Number Revision Date V01.00 13 Oct. 2005 Initial version V01.01 04 Mar. 2008 corrected reference to DJM bit 10.1 Sections Affected Description of Changes Introduction The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 10.1.
PAGE 272
Analog-to-Digital Converter (ADC12B16CV1) 10.1.2 10.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 10.1.2.2 • • • MCU Operating Modes Stop Mode — ICLKSTP=0 (in ATDCTL2 register) Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode.
PAGE 273
Analog-to-Digital Converter (ADC12B16CV1) 10.1.
PAGE 274
Analog-to-Digital Converter (ADC12B16CV1) 10.1.
PAGE 275
Analog-to-Digital Converter (ADC12B16CV1) 10.2 Signal Description This section lists all inputs to the ADC12B16C block. 10.2.1 Detailed Signal Descriptions 10.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 10.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
PAGE 276
Analog-to-Digital Converter (ADC12B16CV1) Address Name 0x0000 ATDCTL0 0x0001 ATDCTL1 0x0002 ATDCTL2 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDCMPEH 0x0009 ATDCMPEL 0x000A ATDSTAT2H 0x000B ATDSTAT2L 0x000C ATDDIENH 0x000D ATDDIENL 0x000E ATDCMPHTH 0x000F ATDCMPHTL 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 Bit 7 R Reserved W R ETRIGSEL W R 0 W R DJM W R SMP2 W
PAGE 277
Analog-to-Digital Converter (ADC12B16CV1) Address Name 0x001E ATDDR7 0x0020 ATDDR8 0x0022 ATDDR9 0x0024 ATDDR10 0x0026 ATDDR11 0x0028 ATDDR12 0x002A ATDDR13 0x002C ATDDR14 0x002E ATDDR15 Bit 7 R W R W R W R W R W R W R W R W R W 6 5 4 3 2 1 See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)” Bit 0 See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 10.3.2.12.
PAGE 278
Analog-to-Digital Converter (ADC12B16CV1) Table 10-3. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting WRAP3 WRAP2 WRAP1 WRAP0 1If 10.3.2.
PAGE 279
Analog-to-Digital Converter (ADC12B16CV1) Table 10-4. ATDCTL1 Field Descriptions Field Description 7 ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0 inputs.
PAGE 280
Analog-to-Digital Converter (ADC12B16CV1) Table 10-6. External Trigger Channel Select Coding 1 ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is 1 0 0 1 0 ETRIG21 1 0 0 1 1 ETRIG31 1 0 1 X X Reserved 1 1 X X X Reserved Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 10.3.2.
PAGE 281
Analog-to-Digital Converter (ADC12B16CV1) Table 10-7. ATDCTL2 Field Descriptions (continued) Field Description 4 ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 10-8 for details. 3 ETRIGP External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 10-8 for details.
PAGE 282
Analog-to-Digital Converter (ADC12B16CV1) Field Description 7 DJM Result Register Data Justification — Result data format is always unsigned. This bit controls justification of conversion data in the result registers. 0 Left justified data in the result registers. 1 Right justified data in the result registers. Table 10-10 gives examples ATD results for an input signal range between 0 and 5.12 Volts.
PAGE 283
Analog-to-Digital Converter (ADC12B16CV1) Table 10-10. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 12-Bit Codes (transfer curve has 1.25mV offset) (resolution=1.25mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 0 0 0 4095 ... 17 16 14 12 11 9 8 6 4 3 2 1 0 Table 10-11.
PAGE 284
Analog-to-Digital Converter (ADC12B16CV1) Table 10-12. ATD Behavior in Freeze Mode (Breakpoint) 10.3.2.5 FRZ1 FRZ0 1 1 Behavior in Freeze Mode Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 10-8. ATD Control Register 4 (ATDCTL4) Read: Anytime Write: Anytime Table 10-13.
PAGE 285
Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.6 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase.
PAGE 286
Analog-to-Digital Converter (ADC12B16CV1) Table 10-16.
PAGE 287
Analog-to-Digital Converter (ADC12B16CV1) Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 10-17. ATDSTAT0 Field Descriptions Field Description 7 SCF Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the flag is set after each one is completed.
PAGE 288
Analog-to-Digital Converter (ADC12B16CV1) Module Base + 0x0008 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CMPE[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 Figure 10-11. ATD Compare Enable Register (ATDCMPE) Table 10-18.
PAGE 289
Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[15:0]. Module Base + 0x000A 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CCF[15:0] W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-12. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime, no effect Table 10-19.
PAGE 290
Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 IEN[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 Figure 10-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 10-20.
PAGE 291
Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
PAGE 292
Analog-to-Digital Converter (ADC12B16CV1) Table 10-22. Conversion result mapping to ATDDRn A/D resolution 10.4 DJM conversion result mapping to ATDDRn 8-bit data 0 Bit[11:4] = result, Bit[3:0]=0000 8-bit data 1 Bit[7:0] = result, Bit[11:8]=0000 10-bit data 0 Bit[11:2] = result, Bit[1:0]=00 10-bit data 1 Bit[9:0] = result, Bit[11:10]=00 12-bit data X Bit[11:0] = result Functional Description The ADC12B16C is structured into an analog sub-block and a digital sub-block. 10.4.
PAGE 293
Analog-to-Digital Converter (ADC12B16CV1) Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output code. 10.4.2 Digital Sub-Block This subsection explains some of the digital features in more detail. See Section 10.3.2, “Register Descriptions” for all details. 10.4.2.
PAGE 294
Analog-to-Digital Converter (ADC12B16CV1) 10.4.2.2 General-Purpose Digital Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled as analog channels to the A/D converter. The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog input channels of the ADC12B16C. The input pad signal is buffered to the digital port registers.
PAGE 295
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-1. Revision History Revision Number Revision Date V03.11 31 Mar 2009 V03.12 09 Aug 2010 Table 11-37 • Added ‘Bosch CAN 2.0A/B’ to bit time settings table V03.13 03 Mar 2011 Figure 11-4 Table 11-3 • Corrected CANE write restrictions • Removed footnote from RXFRM bit 11.
PAGE 296
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.1.1 Glossary Table 11-2. Terminology ACK Acknowledge of CAN message CAN Controller Area Network CRC Cyclic Redundancy Code EOF End of Frame FIFO First-In-First-Out Memory IFS Inter-Frame Sequence SOF Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock 11.1.
PAGE 297
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.
PAGE 298
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.2 External Signal Description The MSCAN uses two external pins. NOTE On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional. 11.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 11.2.
PAGE 299
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 11.3.1 Module Memory Map Figure 11-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description.
PAGE 300
Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name Bit 7 0x0000 CANCTL0 R 0x0001 CANCTL1 R W W 0x0002 CANBTR0 R 0x0003 CANBTR1 R 0x0004 CANRFLG R 0x0005 CANRIER R 0x0006 CANTFLG R 0x0007 CANTIER 0x0008 CANTARQ W W W W R R W 0x000E CANRXERR SYNCH 3 2 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WUPIF
PAGE 301
Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x000F CANTXERR R 0x0010–0x0013 CANIDAR0–3 R 0x0014–0x0017 CANIDMRx R 0x0018–0x001B CANIDAR4–7 R 0x001C–0x001F CANIDMR4–7 R 0x0020–0x002F CANRXFG R 0x0030–0x003F CANTXFG R Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM
PAGE 302
Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
PAGE 303
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-3. CANCTL0 Register Field Descriptions (continued) Field Description 1 SLPRQ(4) Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 11.4.5.5, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty.
PAGE 304
Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x0001 7 6 5 4 3 2 CANE CLKSRC LOOPB LISTEN BORM WUPM 0 0 0 1 0 0 R 1 0 SLPAK INITAK 0 1 W Reset: = Unimplemented Figure 11-5. MSCAN Control Register 1 (CANCTL1) 1.
PAGE 305
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-4. CANCTL1 Register Field Descriptions (continued) Field Description 1 SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 11.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
PAGE 306
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-7. Baud Rate Prescaler 11.3.2.4 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
PAGE 307
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-9. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle(1) 0 0 1 2 Tq clock cycles : : : : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles 1. This setting is not valid. Please refer to Table 11-37 for valid settings. Table 11-10.
PAGE 308
Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Table 11-11.
PAGE 309
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-11. CANRFLG Register Field Descriptions (continued) Field Description 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected 0 RXF(2) Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
PAGE 310
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-12. CANRIER Register Field Descriptions Field 7 WUPIE(1) 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
PAGE 311
Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x0006 R 7 6 5 4 3 0 0 0 0 0 2 1 0 TXE2 TXE1 TXE0 1 1 1 W Reset: 0 0 0 0 0 = Unimplemented Figure 11-10. MSCAN Transmitter Flag Register (CANTFLG) 1. Read: Anytime Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
PAGE 312
Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 11-14. CANTIER Register Field Descriptions Field Description 2-0 TXEIE[2:0] 11.3.2.
PAGE 313
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Access: User read/write(1) Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 11-13.
PAGE 314
Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 11-17. CANTBSEL Register Field Descriptions Field Description 2-0 TX[2:0] Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g.
PAGE 315
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-18. CANIDAC Register Field Descriptions Field Description 5-4 IDAM[1:0] Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 11.4.3, “Identifier Acceptance Filter”). Table 11-19 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded.
PAGE 316
Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x000C to Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 11-16. MSCAN Reserved Register 1. Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special system operating modes can alter the MSCAN functionality. 11.3.2.
PAGE 317
Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x000E R 7 6 5 4 3 2 1 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 11-18. MSCAN Receive Error Counter (CANRXERR) 1.
PAGE 318
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 11.3.3.
PAGE 319
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-23. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7-0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. 11.3.2.
PAGE 320
Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 11-25. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description 7-0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match.
PAGE 321
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-26.
PAGE 322
Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-24.
PAGE 323
Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued) Register Name Bit 7 6 5 4 3 2 1 Bit0 = Unused, always read ‘x’ Read: • For transmit buffers, anytime when TXEx flag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
PAGE 324
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 x x x x x x x x R W Reset: Figure 11-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 11-27. IDR0 Register Field Descriptions — Extended Field Description 7-0 ID[28:21] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
PAGE 325
Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 7 6 5 4 3 2 1 0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x R W Reset: Figure 11-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 11-29. IDR2 Register Field Descriptions — Extended Field Description 7-0 ID[14:7] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
PAGE 326
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 x x x x x x x x R W Reset: Figure 11-30. Identifier Register 0 — Standard Mapping Table 11-31. IDR0 Register Field Descriptions — Standard Field Description 7-0 ID[10:3] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format.
PAGE 327
Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 11-32. Identifier Register 2 — Standard Mapping Module Base + 0x00X3 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 11-33. Identifier Register 3 — Standard Mapping 11.3.3.
PAGE 328
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. Module Base + 0x00XC 7 6 5 4 3 2 1 0 DLC3 DLC2 DLC1 DLC0 x x x x R W Reset: x x x x = Unused; always read “x” Figure 11-35. Data Length Register (DLR) — Extended Identifier Mapping Table 11-34.
PAGE 329
Freescale’s Scalable Controller Area Network (S12MSCANV3) • The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. Access: User read/write(1) Module Base + 0x00XD 7 6 5 4 3 2 1 0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 0 0 0 0 0 0 0 0 R W Reset: Figure 11-36. Transmit Buffer Priority Register (TBPR) 1.
PAGE 330
Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x00XF R 7 6 5 4 3 2 1 0 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 x x x x x x x x W Reset: Figure 11-38. Time Stamp Register — Low Byte (TSRL) 1. Read: Anytime when TXEx flag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.
PAGE 331
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4 11.4.1 Functional Description General This section provides a complete functional description of the MSCAN. 11.4.2 Message Storage CAN Receive / Transmit Engine Memory Mapped I/O Rx0 RXF CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 Receiver TxBG Tx0 MSCAN TxFG Tx1 Transmitter TxBG Tx2 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 11-39. User Model for Message Buffer Organization S12XS Family Reference Manual Rev. 1.
PAGE 332
Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 11.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages.
PAGE 333
Freescale’s Scalable Controller Area Network (S12MSCANV3) software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
PAGE 334
Freescale’s Scalable Controller Area Network (S12MSCANV3) generates a receive interrupt1 (see Section 11.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG.
PAGE 335
Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Figure 11-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. Four identifier acceptance filters, each to be applied to: — The 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages.
PAGE 336
Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 11-41.
PAGE 337
Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
PAGE 338
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
PAGE 339
Freescale’s Scalable Controller Area Network (S12MSCANV3) For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn. 11-2 f CANCLK = ----------------------------------------------------Tq ( Prescaler value -) A bit time is subdivided into three segments as described in the Bosch CAN 2.
PAGE 340
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-36. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
PAGE 341
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.4.2 Special System Operating Modes The MSCAN module behaves as described within this specification in all special system operating modes. Write restrictions which exist on specific registers in normal modes are lifted for test purposes in special modes. 11.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like in normal system operating modes as described within this specification. 11.4.4.
PAGE 342
Freescale’s Scalable Controller Area Network (S12MSCANV3) Bus Clock Domain CAN Clock Domain INITRQ SYNC sync. INITRQ sync. SYNC INITAK CPU Init Request INITAK Flag INITAK INIT Flag Figure 11-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Figure 11-45).
PAGE 343
Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-38. CPU vs. MSCAN Operating Modes MSCAN Mode Reduced Power Consumption CPU Mode Normal Sleep RUN CSWAI = X(1) SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 WAIT CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 1 SLPAK = 1 STOP Power Down Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X 1.
PAGE 344
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.5.5 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register.
PAGE 345
Freescale’s Scalable Controller Area Network (S12MSCANV3) If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect.
PAGE 346
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.5.7 Disabled Mode The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as specified. 11.4.5.8 Programmable Wake-Up Function The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0).
PAGE 347
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer. 11.4.7.
PAGE 348
Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.5 11.5.1 Initialization/Application Information MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode If the configuration of registers which are only writable in initialization mode shall be changed: 1.
PAGE 349
Chapter 12 Periodic Interrupt Timer (S12PIT24B4CV1) Table 12-1. Revision History Version Number 12.1 Revision Date Effective Date Author Description of Changes 01.00 28-Apr-05 28-Apr-05 Initial Release 01.01 05-Jul-05 Added application section, removed table 1-1 05-Jul-05 Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 12-1 for a simplified block diagram. 12.1.
PAGE 350
Periodic Interrupt Timer (S12PIT24B4CV1) • Run mode This is the basic mode of operation. Wait mode PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register. In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled. Stop mode In full stop mode or pseudo stop mode, the PIT module is stalled.
PAGE 351
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3 Register Definition This section consists of register descriptions in address order of the PIT. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
PAGE 352
Periodic Interrupt Timer (S12PIT24B4CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x000E R PITCNT1 (High) W PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 0x000F R PITCNT1 (Low) W PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0x0010 PITLD2 (High) PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x0012 R PITCNT2 (High) W PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9
PAGE 353
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT) Module Base + 0x0000 R W Reset 7 6 5 PITE PITSWAI PITFRZ 0 0 0 4 3 2 0 0 0 0 0 0 1 0 0 0 PFLMT1 PFLMT0 0 0 = Unimplemented or Reserved Figure 12-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 12-2.
PAGE 354
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.2 PIT Force Load Timer Register (PITFLT) Module Base + 0x0001 R 7 6 5 4 0 0 0 0 W Reset 0 0 0 3 2 1 0 0 0 0 0 PFLT3 PFLT2 PFLT1 PFLT0 0 0 0 0 0 Figure 12-4. PIT Force Load Timer Register (PITFLT) Read: Anytime Write: Anytime Table 12-3.
PAGE 355
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.4 PIT Multiplex Register (PITMUX) Module Base + 0x0003 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PMUX3 PMUX2 PMUX1 PMUX0 0 0 0 0 Figure 12-6. PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime Table 12-5. PITMUX Field Descriptions Field Description 3:0 PMUX[3:0] PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to micro time base 1 or 0.
PAGE 356
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.6 PIT Time-Out Flag Register (PITTF) Module Base + 0x0005 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PTF3 PTF2 PTF1 PTF0 0 0 0 0 Figure 12-8. PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear) Table 12-7.
PAGE 357
Periodic Interrupt Timer (S12PIT24B4CV1) Table 12-8. PITMTLD0–1 Field Descriptions Field Description 7:0 PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers. PMTLD[7:0] Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down to zero, the PMTLD register value will be loaded.
PAGE 358
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.8 PIT Load Register 0 to 3 (PITLD0–3) Module Base + 0x0008, 0x0009 15 R W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 12-11.
PAGE 359
Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.9 PIT Count Register 0 to 3 (PITCNT0–3) Module Base + 0x000A, 0x000B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 12-15.
PAGE 360
Periodic Interrupt Timer (S12PIT24B4CV1) 12.4 Functional Description Figure 12-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface.
PAGE 361
Periodic Interrupt Timer (S12PIT24B4CV1) Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set, as shown in Figure 12-20. The time-out period is a function of the timer load (PITLD) and micro timer load (PITMTLD) registers and the bus clock fBUS: time-out period = (PITMTLD + 1) * (PITLD + 1) / fBUS.
PAGE 362
Periodic Interrupt Timer (S12PIT24B4CV1) is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit. NOTE Be careful when resetting the PITE, PINTE or PITCE bits in case of pending PIT interrupt requests, to avoid spurious interrupt requests. 12.4.3 Hardware Trigger The PIT module contains four hardware trigger signal lines PITTRIG[3:0], one for each timer channel.
PAGE 363
Periodic Interrupt Timer (S12PIT24B4CV1) 12.6 Application Information To get started quickly with the PIT24B8C module this section provides a small code example how to use the block. Please note that the example provided is only one specific case out of the possible configurations and implementations. Functionality: Generate an PIT interrupt on channel 0 every 500 PIT clock cycles.
PAGE 364
Periodic Interrupt Timer (S12PIT24B4CV1) S12XS Family Reference Manual, Rev. 1.
PAGE 365
Chapter 13 Pulse-Width Modulator (S12PWM8B8CV1) Version Revision Number Date 01.17 13.1 Effective Date 08-01-2004 Author Description of Changes Added clarification of PWMIF operation in STOP and WAIT mode. Added notes on minimum pulse width of emergency shutdown signal. Introduction The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.
PAGE 366
Pulse-Width Modulator (S12PWM8B8CV1) 13.1.2 Modes of Operation There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. 13.1.3 Block Diagram Figure 13-1 shows the block diagram for the 8-bit 8-channel PWM block.
PAGE 367
Pulse-Width Modulator (S12PWM8B8CV1) 13.2.1 PWM7 — PWM Channel 7 This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature. 13.2.2 PWM6 — PWM Channel 6 This pin serves as waveform output of PWM channel 6. 13.2.3 PWM5 — PWM Channel 5 This pin serves as waveform output of PWM channel 5. 13.2.4 PWM4 — PWM Channel 4 This pin serves as waveform output of PWM channel 4. 13.2.5 PWM3 — PWM Channel 3 This pin serves as waveform output of PWM channel 3. 13.
PAGE 368
Pulse-Width Modulator (S12PWM8B8CV1) with the PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. . NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 13.3.
PAGE 369
Pulse-Width Modulator (S12PWM8B8CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000A R PWMSCNTA W 1 0 0 0 0 0 0 0 0 0x000B R PWMSCNTB W 1 0 0 0 0 0 0 0 0 0x000C R PWMCNT0 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000D R PWMCNT1 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000E R PWMCNT2 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R 0x000F PWMCNT3 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x0010 R PWMCNT4 W Bit 7 6
PAGE 370
Pulse-Width Modulator (S12PWM8B8CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0019 R PWMPER5 W Bit 7 6 5 4 3 2 1 Bit 0 0x001A R PWMPER6 W Bit 7 6 5 4 3 2 1 Bit 0 0x001B R PWMPER7 W Bit 7 6 5 4 3 2 1 Bit 0 0x001C R PWMDTY0 W Bit 7 6 5 4 3 2 1 Bit 0 0x001D R PWMDTY1 W Bit 7 6 5 4 3 2 1 Bit 0 0x001E R PWMDTY2 W Bit 7 6 5 4 3 2 1 Bit 0 0x001F R PWMDTY3 W Bit 7 6 5 4 3 2 1 Bit 0 0x0010 R PWMDTY4 W Bit 7 6 5 4 3 2 1 Bit 0 0x0021 R PW
PAGE 371
Pulse-Width Modulator (S12PWM8B8CV1) NOTE The first PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled.
PAGE 372
Pulse-Width Modulator (S12PWM8B8CV1) Table 13-1. PWME Field Descriptions (continued) Field Description 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled.
PAGE 373
Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 0 0 0 0 0 0 0 0 Figure 13-5. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 13-3.
PAGE 374
Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0003 7 R 6 0 W Reset 0 5 4 3 PCKB2 PCKB1 PCKB0 0 0 0 0 2 1 0 PCKA2 PCKA1 PCKA0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. PWM Prescale Clock Select Register (PWMPRCLK) Read: Anytime Write: Anytime NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 13-4.
PAGE 375
Pulse-Width Modulator (S12PWM8B8CV1) 13.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See Section 13.4.2.5, “Left Aligned Outputs” and Section 13.4.2.
PAGE 376
Pulse-Width Modulator (S12PWM8B8CV1) 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 13.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. Table 13-8.
PAGE 377
Pulse-Width Modulator (S12PWM8B8CV1) 13.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 13-9. Reserved Register (PWMTST) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.
PAGE 378
Pulse-Width Modulator (S12PWM8B8CV1) NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Module Base + 0x0008 R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 13-11. PWM Scale A Register (PWMSCLA) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value) 13.3.2.
PAGE 379
Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x000A, 0x000B R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 13-13. Reserved Registers (PWMSCNTx) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality. 13.3.2.
PAGE 380
Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime (any value written causes PWM counter to be reset to $00). 13.3.2.13 PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel.
PAGE 381
Pulse-Width Modulator (S12PWM8B8CV1) 13.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state.
PAGE 382
Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime 13.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. Module Base + 0x0024 7 R W Reset PWMIF 0 6 5 PWMIE 0 0 PWMRSTRT 0 4 PWMLVL 0 3 2 0 PWM7IN 0 0 1 0 PWM7INL PWM7ENA 0 0 = Unimplemented or Reserved Figure 13-17.
PAGE 383
Pulse-Width Modulator (S12PWM8B8CV1) 13.4 Functional Description 13.4.1 PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
PAGE 384
Pulse-Width Modulator (S12PWM8B8CV1) Clock A PCKA2 PCKA1 PCKA0 Clock A/2, A/4, A/6,....A/512 8-Bit Down Counter M U X Load DIV 2 Clock to PWM Ch 0 PCLK0 Count = 1 PWMSCLA M U X Clock SA PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 M U X 2 4 8 16 32 64 128 Divide by Prescaler Taps: X PCLK3 Clock B Clock B/2, B/4, B/6,....
PAGE 385
Pulse-Width Modulator (S12PWM8B8CV1) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register.
PAGE 386
Pulse-Width Modulator (S12PWM8B8CV1) 13.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period.
PAGE 387
Pulse-Width Modulator (S12PWM8B8CV1) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 13.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal.
PAGE 388
Pulse-Width Modulator (S12PWM8B8CV1) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops.
PAGE 389
Pulse-Width Modulator (S12PWM8B8CV1) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 13-20.
PAGE 390
Pulse-Width Modulator (S12PWM8B8CV1) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 13-21. PWM Left Aligned Output Example Waveform 13.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00.
PAGE 391
Pulse-Width Modulator (S12PWM8B8CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
PAGE 392
Pulse-Width Modulator (S12PWM8B8CV1) As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 13-23 is the output waveform generated. E = 100 ns E = 100 ns DUTY CYCLE = 75% PERIOD = 800 ns Figure 13-23. PWM Center Aligned Output Example Waveform 13.4.2.
PAGE 393
Pulse-Width Modulator (S12PWM8B8CV1) Clock Source 7 High Low PWMCNT6 PWCNT7 Period/Duty Compare PWM7 Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 13-24.
PAGE 394
Pulse-Width Modulator (S12PWM8B8CV1) Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 13-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 13-11. 16-bit Concatenation Mode Summary 13.4.2.
PAGE 395
Pulse-Width Modulator (S12PWM8B8CV1) 13.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active.
PAGE 396
Pulse-Width Modulator (S12PWM8B8CV1) S12XS Family Reference Manual, Rev. 1.
PAGE 397
Chapter 14 Serial Communication Interface (S12SCIV5) Table 14-1. Revision History Version Revision Effective Number Date Date 05.03 12/25/2008 Author Description of Changes 05.04 08/05/2009 remove redundancy comments in Figure1-2 fix typo, SCIBDL reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, Table 14-4,SCICR1 Even parity should be PT=0 fix typo, on page 14-419,should be BKDIF,not BLDIF 14.
PAGE 398
Serial Communication Interface (S12SCIV5) 14.1.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
PAGE 399
Serial Communication Interface (S12SCIV5) 14.1.4 Block Diagram Figure 14-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
PAGE 400
Serial Communication Interface (S12SCIV5) 14.2 External Signal Description The SCI module has a total of two external pins. 14.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 14.2.2 RXD — Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high.
PAGE 401
Serial Communication Interface (S12SCIV5) 14.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
PAGE 402
Serial Communication Interface (S12SCIV5) 14.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Module Base + 0x0000 R W Reset 7 6 5 4 3 2 1 0 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 Figure 14-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 R W Reset 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 Figure 14-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0.
PAGE 403
Serial Communication Interface (S12SCIV5) Table 14-3. IRSCI Transmit Pulse Width 14.3.2.2 TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 SCI Control Register 1 (SCICR1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Figure 14-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition).
PAGE 404
Serial Communication Interface (S12SCIV5) Table 14-4. SCICR1 Field Descriptions (continued) Field Description 2 ILT Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character.
PAGE 405
Serial Communication Interface (S12SCIV5) 14.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x0000 7 R W Reset RXEDGIF 0 6 5 4 3 2 0 0 0 0 BERRV 0 0 0 0 0 1 0 BERRIF BKDIF 0 0 = Unimplemented or Reserved Figure 14-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-6.
PAGE 406
Serial Communication Interface (S12SCIV5) 14.3.2.4 SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x0001 7 R W Reset RXEDGIE 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 BERRIE BKDIE 0 0 = Unimplemented or Reserved Figure 14-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-7.
PAGE 407
Serial Communication Interface (S12SCIV5) 14.3.2.5 SCI Alternative Control Register 2 (SCIACR2) Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 W Reset 0 2 1 0 BERRM1 BERRM0 BKDFE 0 0 0 = Unimplemented or Reserved Figure 14-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-8.
PAGE 408
Serial Communication Interface (S12SCIV5) 14.3.2.6 SCI Control Register 2 (SCICR2) Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 14-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 14-10. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
PAGE 409
Serial Communication Interface (S12SCIV5) 14.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.
PAGE 410
Serial Communication Interface (S12SCIV5) Table 14-11. SCISR1 Field Descriptions (continued) Field Description 3 OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
PAGE 411
Serial Communication Interface (S12SCIV5) 14.3.2.8 SCI Status Register 2 (SCISR2) Module Base + 0x0005 7 R W Reset AMAP 0 6 5 0 0 0 0 4 3 2 1 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 RAF 0 = Unimplemented or Reserved Figure 14-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 14-12. SCISR2 Field Descriptions Field Description 7 AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible.
PAGE 412
Serial Communication Interface (S12SCIV5) 14.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Module Base + 0x0006 7 R 6 R8 W Reset 0 T8 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 14-13.
PAGE 413
Serial Communication Interface (S12SCIV5) 14.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 14-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
PAGE 414
Serial Communication Interface (S12SCIV5) 14.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s.
PAGE 415
Serial Communication Interface (S12SCIV5) 14.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 14-15 below.
PAGE 416
Serial Communication Interface (S12SCIV5) 1 14.4.4 The address bit identifies the frame as an address character. See Section 14.4.6.6, “Receiver Wakeup”. Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL).
PAGE 417
Serial Communication Interface (S12SCIV5) 14.4.
PAGE 418
Serial Communication Interface (S12SCIV5) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate.
PAGE 419
Serial Communication Interface (S12SCIV5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out.
PAGE 420
Serial Communication Interface (S12SCIV5) Figure 14-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission.
PAGE 421
Serial Communication Interface (S12SCIV5) 14.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 14-18.
PAGE 422
Serial Communication Interface (S12SCIV5) 14.4.
PAGE 423
Serial Communication Interface (S12SCIV5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 14.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
PAGE 424
Serial Communication Interface (S12SCIV5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-18 summarizes the results of the data bit samples. Table 14-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
PAGE 425
Serial Communication Interface (S12SCIV5) In Figure 14-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
PAGE 426
Serial Communication Interface (S12SCIV5) In Figure 14-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
PAGE 427
Serial Communication Interface (S12SCIV5) Figure 14-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
PAGE 428
Serial Communication Interface (S12SCIV5) 14.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values.
PAGE 429
Serial Communication Interface (S12SCIV5) 14.4.6.5.2 Fast Data Tolerance Figure 14-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 14-29.
PAGE 430
Serial Communication Interface (S12SCIV5) 14.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state.
PAGE 431
Serial Communication Interface (S12SCIV5) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
PAGE 432
Serial Communication Interface (S12SCIV5) 14.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE.
PAGE 433
Serial Communication Interface (S12SCIV5) 14.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 14.5.3.1.
PAGE 434
Serial Communication Interface (S12SCIV5) 14.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 14.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected.
PAGE 435
Chapter 15 Serial Peripheral Interface (S12SPIV5) Table 15-1. Revision History Revision Number Revision Date Sections Affected V05.00 24 Mar 2005 15.3.2/15-439 15.1 Description of Changes - Added 16-bit transfer width feature. Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 15.1.1 Glossary of Terms SPI SS SCK MOSI MISO MOMI SISO 15.1.
PAGE 436
Serial Peripheral Interface (S12SPIV5) • • • Run mode This is the basic mode of operation. Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off.
PAGE 437
Serial Peripheral Interface (S12SPIV5) SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register SPIF MODF SPTEF Slave Control CPOL CPHA Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Interrupt Control SPI Interrupt Request Baud Rate Generator Master Control Counter Bus Clock Prescaler Clock Select SPPR 3 SPR MOSI Port Control Logic SCK SS Baud Rate Shift Clock Sample Clock 3 Shifter SPI Baud Rate Register Da
PAGE 438
Serial Peripheral Interface (S12SPIV5) 15.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave. 15.2.4 SCK — Serial Clock Pin In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock. 15.
PAGE 439
Serial Peripheral Interface (S12SPIV5) 15.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. 15.3.2.1 SPI Control Register 1 (SPICR1) Module Base +0x0000 R W Reset 7 6 5 4 3 2 1 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 0 0 1 0 0 Figure 15-3.
PAGE 440
Serial Peripheral Interface (S12SPIV5) Table 15-2. SPICR1 Field Descriptions (continued) Field Description 1 SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 15-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 LSBFE LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register.
PAGE 441
Serial Peripheral Interface (S12SPIV5) Table 15-4. SPICR2 Field Descriptions Field Description 6 XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Please refer to Section 15.3.2.
PAGE 442
Serial Peripheral Interface (S12SPIV5) 15.3.2.3 SPI Baud Rate Register (SPIBR) Module Base +0x0002 7 R 0 W Reset 0 6 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 = Unimplemented or Reserved Figure 15-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 15-6.
PAGE 443
Serial Peripheral Interface (S12SPIV5) Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3) Baud Rate Divisor Baud Rate 0 64 390.63 kbit/s 1 128 195.31 kbit/s 1 0 256 97.66 kbit/s 1 1 512 48.83 kbit/s 0 0 0 6 4.16667 Mbit/s 0 0 1 12 2.08333 Mbit/s 0 0 1 0 24 1.04167 Mbit/s 0 0 1 1 48 520.83 kbit/s 1 0 1 0 0 96 260.42 kbit/s 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.
PAGE 444
Serial Peripheral Interface (S12SPIV5) Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3) Baud Rate Divisor Baud Rate 0 896 27.90 kbit/s 1 1792 13.95 kbit/s 0 0 16 1.5625 Mbit/s 0 1 32 781.25 kbit/s 0 1 0 64 390.63 kbit/s 0 1 1 128 195.31 kbit/s 1 1 0 0 256 97.66 kbit/s 1 1 0 1 512 48.83 kbit/s 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 2048 12.
PAGE 445
Serial Peripheral Interface (S12SPIV5) Table 15-9. SPIF Interrupt Flag Clearing Sequence XFRW Bit SPIF Interrupt Flag Clearing Sequence 0 Read SPISR with SPIF == 1 1 Read SPISR with SPIF == 1 then Read SPIDRL Byte Read SPIDRL 1 or then Byte Read SPIDRH 2 Byte Read SPIDRL or Word Read (SPIDRH:SPIDRL) 1 2 Data in SPIDRH is lost in this case. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF == 1. Table 15-10.
PAGE 446
Serial Peripheral Interface (S12SPIV5) 15.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL) Module Base +0x0004 7 6 5 4 3 2 1 0 R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 0 0 0 0 0 0 0 0 Reset Figure 15-7. SPI Data Register High (SPIDRH) Module Base +0x0005 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 15-8.
PAGE 447
Serial Peripheral Interface (S12SPIV5) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data B Data A = Unspecified Data C = Reception in progress Figure 15-9. Reception with SPIF serviced in Time Data A Received Data B Received Data C Received Data B Lost SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data A = Unspecified Data C = Reception in progress Figure 15-10.
PAGE 448
Serial Peripheral Interface (S12SPIV5) The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1 register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions by the S-clock from the master, so data is exchanged between the master and the slave.
PAGE 449
Serial Peripheral Interface (S12SPIV5) drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
PAGE 450
Serial Peripheral Interface (S12SPIV5) As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched.
PAGE 451
Serial Peripheral Interface (S12SPIV5) The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device.
PAGE 452
Serial Peripheral Interface (S12SPIV5) End of Idle State Begin 1 SCK Edge Number 2 3 4 5 6 7 8 Begin of Idle State End Transfer 9 10 11 12 13 14 15 16 Bit 1 Bit 6 LSB Minimum 1/2 SCK for tT, tl, tL MSB SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum lea
PAGE 453
Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) MSB first (LSBFE = 0) LSB first (LSBFE = 1) tL tT tI tL MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit
PAGE 454
Serial Peripheral Interface (S12SPIV5) When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
PAGE 455
Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tI tL Minimum 1/2 SCK for tT, tl, tL tL MSB first (LSBFE = 0) LSB first (LSBFE = 1) MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 B
PAGE 456
Serial Peripheral Interface (S12SPIV5) When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc.
PAGE 457
Serial Peripheral Interface (S12SPIV5) Table 15-11. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode SPC0 = 0 MOSI MOSI Serial In SPI SPI Serial In MISO Serial Out Bidirectional Mode SPC0 = 1 Slave Mode MSTR = 0 MOMI Serial Out MISO Serial In BIDIROE SPI BIDIROE Serial In SPI Serial Out SISO The direction of each serial I/O pin depends on the BIDIROE bit.
PAGE 458
Serial Peripheral Interface (S12SPIV5) the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state.
PAGE 459
Serial Peripheral Interface (S12SPIV5) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode.
PAGE 460
Serial Peripheral Interface (S12SPIV5) 15.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”. 15.4.7.5.3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced.
PAGE 461
Chapter 16 Timer Module (TIM16B8CV2) Table 16-1. Revision History Revision Number Revision Date Sections Affected V02.05 9 Jul 2009 16.3.2.12/16-477 16.3.2.13/16-477 16.3.2.15/16-479 16.3.2.16/16-480 16.3.2.19/16-482 16.4.2/16-485 16.4.3/16-485 - Revised flag clearing procedure, whereby TEN or PAEN bit must be set when clearing flags. - Add fomula to describe prescaler V02.06 26 Aug 2009 16.1.2/16-462 16.3.2.15/16-479 16.3.2.2/16-468 16.3.2.3/16-469 16.3.2.4/16-470 16.4.
PAGE 462
Timer Module (TIM16B8CV2) • • • • Eight input capture/output compare channels. Clock prescaling. 16-bit counter. 16-bit pulse accumulator. 16.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keep on running, unless TSFRZ in TSCR1 (0x0006) is set to 1. Wait: Counters keep on running, unless TSWAI in TSCR1 (0x0006) is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 (0x0006) is cleared to 0. S12XS Family Reference Manual, Rev. 1.
PAGE 463
Timer Module (TIM16B8CV2) 16.1.
PAGE 464
Timer Module (TIM16B8CV2) TIMCLK (Timer clock) CLK1 CLK0 Intermodule Bus Clock select (PAMOD) Edge detector PT7 PACLK PACLK / 256 PACLK / 65536 Prescaled clock (PCLK) 4:1 MUX Interrupt PACNT MUX Divide by 64 M clock Figure 16-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer PTn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 16-3. Interrupt Flag Setting S12XS Family Reference Manual, Rev. 1.
PAGE 465
Timer Module (TIM16B8CV2) PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OCPD TEN TIOS7 Figure 16-4. Channel 7 Output Compare/Pulse Accumulator Logic 16.2 External Signal Description The TIM16B8CV2 module has a total of eight external pins. 16.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin This pin serves as input capture or output compare for channel 7. This can also be configured as pulse accumulator input. 16.2.
PAGE 466
Timer Module (TIM16B8CV2) 16.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin This pin serves as input capture or output compare for channel 1. 16.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin This pin serves as input capture or output compare for channel 0. NOTE For the description of interrupts see Section 16.6, “Interrupts”. 16.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 16.3.
PAGE 467
Timer Module (TIM16B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0x0006 TSCR1 R W TEN TSWAI TSFRZ TFFCA PRNT 0x0007 TTOV R W TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 0x0008 TCTL1 R W OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0x0009 TCTL2 R W OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0x000A TCTL3 R W EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0x000B TCTL4 R W EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0x000C TIE R W C7I C6I C5I C4I C3I C2
PAGE 468
Timer Module (TIM16B8CV2) Register Name 0x002C OCPD R W 0x002D R 0x002E PTPSR R W 0x002F Reserved R W Bit 7 6 5 4 3 2 1 Bit 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 = Unimplemented or Reserved Figure 16-5. TIM16B8CV2 Register Summary (Sheet 3 of 3) 16.3.2.
PAGE 469
Timer Module (TIM16B8CV2) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 16-3. CFORC Field Descriptions Field Description 7:0 FOC[7:0] Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately.
PAGE 470
Timer Module (TIM16B8CV2) 16.3.2.4 Output Compare 7 Data Register (OC7D) Module Base + 0x0003 7 6 5 4 3 2 1 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 R W Reset Figure 16-9. Output Compare 7 Data Register (OC7D) Read: Anytime Write: Anytime Table 16-5.
PAGE 471
Timer Module (TIM16B8CV2) Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 16.3.2.6 Timer System Control Register 1 (TSCR1) Module Base + 0x0006 7 6 5 4 3 TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 0 0 R 2 1 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 16-12.
PAGE 472
Timer Module (TIM16B8CV2) Table 16-6. TSCR1 Field Descriptions (continued) Field Description 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag.
PAGE 473
Timer Module (TIM16B8CV2) 16.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 R W Reset Figure 16-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 R W Reset Figure 16-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 16-8.
PAGE 474
Timer Module (TIM16B8CV2) To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the OC7M register must also be cleared. To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in the OC7M register must also be cleared. The settings for these bits can be seen in Table 16-10 Table 16-10.
PAGE 475
Timer Module (TIM16B8CV2) Read: Anytime Write: Anytime. Table 16-11. TCTL3/TCTL4 Field Descriptions Field 7:0 EDGnB EDGnA Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits. Table 16-12. Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) 16.3.2.
PAGE 476
Timer Module (TIM16B8CV2) 16.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R 6 5 4 0 0 0 TOI 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 16-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Table 16-14. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set.
PAGE 477
Timer Module (TIM16B8CV2) NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 16.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 R W Reset Figure 16-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared).
PAGE 478
Timer Module (TIM16B8CV2) Table 16-17. TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation.) 16.3.2.
PAGE 479
Timer Module (TIM16B8CV2) 16.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 R 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 W Reset 0 Unimplemented or Reserved Figure 16-24. 16-Bit Pulse Accumulator Control Register (PACTL) When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7. Read: Any time Write: Any time Table 16-18.
PAGE 480
Timer Module (TIM16B8CV2) Table 16-19. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler. Table 16-20.
PAGE 481
Timer Module (TIM16B8CV2) Table 16-21. PAFLG Field Descriptions Field Description 1 PAOVF Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.
PAGE 482
Timer Module (TIM16B8CV2) 16.3.2.18 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C 7 6 5 4 3 2 1 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 0 0 0 0 R W Reset Figure 16-28. Ouput Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 16-22. OCPD Field Description Field OCPD[7:0} Description Output Compare Pin Disconnect Bits 0 Enables the timer channel port.
PAGE 483
Timer Module (TIM16B8CV2) Table 16-23. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 16-24 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
PAGE 484
Timer Module (TIM16B8CV2) Bus Clock CLK[1:0] PR[2:1:0] channel 7 output compare PACLK PACLK/256 PACLK/65536 MUX TCRE PRESCALER CxI TCNT(hi):TCNT(lo) CxF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR OM:OL0 TC0 EDG0A C0F C0F EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE TOV0 IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR OM:OL1 EDGE DETECT EDG1B EDG1A C1F C1F TC1 CH. 1 CAPTURE IOC1 PIN LOGIC CH.
PAGE 485
Timer Module (TIM16B8CV2) The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced.
PAGE 486
Timer Module (TIM16B8CV2) Note: in Figure 16-31,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock Figure 16-31. The TCNT cycle diagram under TCRE=1 condition prescaler counter TC7 1 bus clock 0 1 TC7-1 TC7 0 TC7 event TC7 event 16.4.3.1 ----- OC Channel Initialization Internal register whose output drives OCx can be programmed before timer drives OCx.
PAGE 487
Timer Module (TIM16B8CV2) NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear. 16.4.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock.
PAGE 488
Timer Module (TIM16B8CV2) 16.6.1 Channel [7:0] Interrupt (C[7:0]F) This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be serviced by the system controller. 16.6.2 Pulse Accumulator Input Interrupt (PAOVI) This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller. 16.6.
PAGE 489
Chapter 17 Voltage Regulator (S12VREGL3V3V1) Table 17-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) Sections Affected Substantial Change(s) V01.02 09 Sep 2005 Updates for API external access and LVR flags. V01.03 23 Sep 2005 VAE reset value is 1. V01.04 08 Jun 2007 Added temperature sensor to customer information 17.1 Introduction Module VREG_3V3 is a tri output voltage regulator that provides two separate 1.
PAGE 490
Voltage Regulator (S12VREGL3V3V1) 3. Shutdown mode Controlled by VREGEN (see device level specification for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a highimpedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API internal RC oscillator clock is not available. This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the VREG_3V3 to use external supplies. 17.1.
PAGE 491
Voltage Regulator (S12VREGL3V3V1) Figure 17-1. VREG_3V3 Block Diagram VBG VDDPLL REG3 VSSPLL REG VDDR VDDA VDDF REG2 VSSA VDD REG1 VSS LVD LVR LVR POR POR VDDX C HTD VREGEN CTRL API Rate Select HTI LVI API API Bus Clock LVD: Low Voltage Detect REG: Regulator Core LVR: Low Voltage Reset CTRL: Regulator Control POR: Power-on Reset API: Auto. Periodical Interrupt HTD: High Temperature Detect PIN S12XS Family Reference Manual, Rev. 1.
PAGE 492
Voltage Regulator (S12VREGL3V3V1) 17.2 External Signal Description Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. Table 17-2 shows all signals of VREG_3V3 associated with pins. Table 17-2.
PAGE 493
Voltage Regulator (S12VREGL3V3V1) In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator. 17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic). In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator. 17.2.
PAGE 494
Voltage Regulator (S12VREGL3V3V1) 17.3.1 Module Memory Map A summary of the registers associated with the VREG_3V3 sub-block is shown in Table 17-3.
PAGE 495
Voltage Regulator (S12VREGL3V3V1) 17.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their individual bits. 17.3.2.1 High Temperature Control Register (VREGHTCL) The VREGHTCL register allows to configure the VREG temperature sense features. 0x02F0 R 7 6 0 0 W Reset 0 0 5 4 3 VSEL VAE HTEN 0 1 0 2 1 0 HTIE HTIF 0 0 HTDS 0 = Unimplemented or Reserved Table 17-4.
PAGE 496
Voltage Regulator (S12VREGL3V3V1) 17.3.2.2 Control Register (VREGCTRL) The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features. 0x02F1 R 7 6 5 4 3 2 0 0 0 0 0 LVDS 0 0 0 0 0 W Reset 0 1 0 LVIE LVIF 0 0 = Unimplemented or Reserved Figure 17-2. Control Register (VREGCTRL) Table 17-5. VREGCTRL Field Descriptions Field Description 2 LVDS Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
PAGE 497
Voltage Regulator (S12VREGL3V3V1) 17.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL) The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt features. 0x02F2 7 R W Reset APICLK 0 6 5 0 0 0 0 4 3 2 1 0 APIES APIEA APIFE APIE APIF 0 0 0 0 0 = Unimplemented or Reserved Figure 17-3. Autonomous Periodical Interrupt Control Register (VREGAPICL) Table 17-6.
PAGE 498
Voltage Regulator (S12VREGL3V3V1) 17.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR) The VREGAPITR register allows to trim the API timeout period. 0x02F3 7 R W Reset 6 5 4 3 2 APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 01 01 01 01 01 01 1 0 0 0 0 0 1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details. = Unimplemented or Reserved Figure 17-4. Autonomous Periodical Interrupt Trimming Register (VREGAPITR) Table 17-7.
PAGE 499
Voltage Regulator (S12VREGL3V3V1) 17.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous periodical interrupt rate. 0x02F4 R W Reset 7 6 5 4 3 2 1 0 APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-5.
PAGE 500
Voltage Regulator (S12VREGL3V3V1) Table 17-10. Selectable Autonomous Periodical Interrupt Periods APICLK APIR[15:0] Selected Period 0 0000 0.2 ms1 0 0001 0.4 ms1 0 0002 0.6 ms1 0 0003 0.8 ms1 0 0004 1.0 ms1 0 0005 1.2 ms1 0 ..... 0 FFFD 13106.8 ms1 0 FFFE 13107.0 ms1 0 FFFF 13107.2 ms1 1 0000 2 * bus clock period 1 0001 4 * bus clock period 1 0002 6 * bus clock period 1 0003 8 * bus clock period 1 0004 10 * bus clock period 1 0005 12 * bus clock period 1 .
PAGE 501
Voltage Regulator (S12VREGL3V3V1) 17.3.2.6 Reserved 06 The Reserved 06 is reserved for test purposes. 0x02F6 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 17-7. Reserved 06 17.3.2.7 High Temperature Trimming Register (VREGHTTR) The VREGHTTR register allows to trim the VREG temperature sense. Fiption 0x02F7 7 R W Reset HTOEN 0 6 5 4 0 0 0 0 0 0 3 2 1 0 HTTR3 HTTR2 HTTR1 HTTR0 01 01 01 01 1.
PAGE 502
Voltage Regulator (S12VREGL3V3V1) 17.4 Functional Description 17.4.1 General Module VREG_3V3 is a voltage regulator, as depicted in Figure 17-1. The regulator functional elements are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on reset module (POR), and a low-voltage reset module (LVR)and a high temperature sensor (HTD). 17.4.2 Regulator Core (REG) Respectively its regulator core has three parallel, independent regulation loops (REG1,REG2 and REG3).
PAGE 503
Voltage Regulator (S12VREGL3V3V1) corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full Performance Mode. 17.4.6 HTD - High Temperature Detect Subblock HTD is responsible for generating the high temperature interrupt (HTI). HTD monitors the die temperature TDIE and continuously updates the status flag HTDS. Interrupt flag HTIF is set whenever status flag HTDS changes its value.
PAGE 504
Voltage Regulator (S12VREGL3V3V1) It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If APIES is set, then at the external pin a clock is visible with 2 times the selected API Period (Table 17-10). If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the size of half of the min period (Table 17-10).
PAGE 505
Voltage Regulator (S12VREGL3V3V1) 17.4.11.1 Low-Voltage Interrupt (LVI) In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. NOTE On entering the Reduced Power Mode, the LVIF is not cleared by the VREG_3V3. 17.4.11.
PAGE 506
Voltage Regulator (S12VREGL3V3V1) S12XS Family Reference Manual, Rev. 1.
PAGE 507
Chapter 18 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-1. Revision History Revision Number Revision Date V01.04 03 Jan 2008 V01.05 19 Dec 2008 18.1/18-507 18.4.2.4/18-542 18.4.2.6/18-544 18.4.2.11/18-54 7 18.4.2.11/18-54 7 18.4.2.11/18-54 7 V01.06 25 Sep 2009 The following changes were made to clarify module behavior related to Flash register access during reset sequence and while Flash commands are active: 18.3.2/18-514 - Add caution concerning register writes while command is active 18.3.2.
PAGE 508
256 KByte Flash Module (S12XFTMR256K1V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
PAGE 509
256 KByte Flash Module (S12XFTMR256K1V1) • • • Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Flexible protection scheme to prevent accidental program or erase of P-Flash memory 18.1.2.
PAGE 510
256 KByte Flash Module (S12XFTMR256K1V1) Flash Interface Command Interrupt Request Registers Error Interrupt Request Protection 16bit internal bus P-Flash 32Kx72 16Kx72 16Kx72 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127 Security Oscillator Clock (XTAL) CPU Clock Divider FCLK Memory Controller D-Flash 4Kx22 Scratch RAM 384x16 sector 0 sector 1 sector 31 Figure 18-1. FTMR256K1 Block Diagram 18.
PAGE 511
256 KByte Flash Module (S12XFTMR256K1V1) 18.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x7C_0000 and 0x7F_FFFF as shown in Table 18-2. The P-Flash memory map is shown in Figure 18-2. Table 18-2. P-Flash Memory Addressing Global Address Size (Bytes) 0x7C_0000 – 0x7F_FFFF 256 K Description P-Flash Block 0 Contains Flash Configuration Field (see Table 18-3) The FPROT register, described in Section 18.3.2.
PAGE 512
256 KByte Flash Module (S12XFTMR256K1V1) P-Flash START = 0x7C_0000 Flash Protected/Unprotected Region 224 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 18-2.
PAGE 513
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 18.4.2.6, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 18-5.
PAGE 514
256 KByte Flash Module (S12XFTMR256K1V1) D-Flash START = 0x10_0000 D-Flash Memory 8 Kbytes D-Flash END = 0x10_1FFF 0x12_0000 D-Flash Nonvolatile Information Register (DFIFRON) 128 bytes 0x12_1000 0x12_2000 Memory Controller Scratch RAM (MGRAMON) 768 bytes 0x12_4000 0x12_E800 0x12_FFFF Figure 18-3. D-Flash and Memory Controller Resource Memory Map 18.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013.
PAGE 515
256 KByte Flash Module (S12XFTMR256K1V1) Address & Name 0x0002 FCCOBIX 0x0003 FECCRIX 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 DFPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV0 0x000D FRSV1 0x000E FECCRHI 0x000F FECCRLO R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX2 CCOBIX1 CCOBIX0 ECCRIX2 ECCRIX1 ECCRIX0 FDFD FSFD DFDIE SFDIE MGSTAT1 MGSTAT0 DFDIF SFDIF W R 0 0 0 0 0 W R 0 0 CCIE 0 0 IGNSF W R 0 W R 0 CCIF ACCERR FPVIOL 0 0 MGBUSY
PAGE 516
256 KByte Flash Module (S12XFTMR256K1V1) Address & Name 0x0010 FOPT 0x0011 FRSV2 0x0012 FRSV3 0x0013 FRSV4 R 7 6 5 4 3 2 1 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W = Unimplemented or Reserved Figure 18-4. FTMR256K1 Register Summary (continued) 18.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
PAGE 517
256 KByte Flash Module (S12XFTMR256K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. S12XS Family Reference Manual, Rev. 1.
PAGE 518
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-7. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) 1 2 MIN1 MAX 1.60 2.10 2.40 FDIV[6:0] 2 OSCCLK Frequency (MHz) FDIV[6:0] MIN1 2 MAX 0x01 33.60 34.65 0x20 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.
PAGE 519
256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 18-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 520
256 KByte Flash Module (S12XFTMR256K1V1) 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 18.5. 18.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX[2:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-7.
PAGE 521
256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-9.
PAGE 522
256 KByte Flash Module (S12XFTMR256K1V1) Offset Module Base + 0x0005 7 6 R 5 4 3 2 1 0 DFDIE SFDIE 0 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 18-14.
PAGE 523
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 524
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
PAGE 525
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 18-18 for the P-Flash block.
PAGE 526
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x7F_8000–0x7F_83FF 1 Kbyte 01 0x7F_8000–0x7F_87FF 2 Kbytes 10 0x7F_8000–0x7F_8FFF 4 Kbytes 11 0x7F_8000–0x7F_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 18-14. Although the protection scheme is loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user.
PAGE 527
FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 Scenario 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] FPLS[1:0] FLASH START FPOPEN = 1 256 KByte Flash Module (S12XFTMR256K1V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 18-14.
PAGE 528
256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 18-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 18-21.
PAGE 529
256 KByte Flash Module (S12XFTMR256K1V1) P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the D-Flash memory fully protected. Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the D-Flash memory is not possible if any of the D-Flash sectors are protected. Table 18-22.
PAGE 530
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-23.
PAGE 531
256 KByte Flash Module (S12XFTMR256K1V1) (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 18-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller.
PAGE 532
256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.13 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-19. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 18.3.2.
PAGE 533
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-25. FECCR Index Settings ECCRIX[2:0] 000 FECCR Register Content Bits [15:8] Bit[7] Bits[6:0] Parity bits read from Flash block 0 Global address [22:16] 001 Global address [15:0] 010 Data 0 [15:0] 011 Data 1 [15:0] (P-Flash only) 100 Data 2 [15:0] (P-Flash only) 101 Data 3 [15:0] (P-Flash only) 110 Not used, returns 0x0000 when read 111 Not used, returns 0x0000 when read Table 18-26.
PAGE 534
256 KByte Flash Module (S12XFTMR256K1V1) During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 18-3) as indicated by reset condition F in Figure 18-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. Table 18-27.
PAGE 535
256 KByte Flash Module (S12XFTMR256K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-25. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 18.4 Functional Description 18.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 536
256 KByte Flash Module (S12XFTMR256K1V1) 18.4.1.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 18.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence.
PAGE 537
256 KByte Flash Module (S12XFTMR256K1V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 538
256 KByte Flash Module (S12XFTMR256K1V1) 18.4.1.3 Valid Flash Module Commands Table 18-28. Flash Commands by Mode Unsecured FCMD 1 2 3 4 5 6 7 8 18.4.1.
PAGE 539
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-29. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0 that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and D-Flash) blocks.
PAGE 540
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-30. D-Flash Commands FCMD Command Function on D-Flash Memory 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks and verifying that all D-Flash (and P-Flash) blocks are erased. 0x0D Set User Margin Level Specifies a user margin read level for the D-Flash block. 0x0E Set Field Margin Level Specifies a field margin read level for the D-Flash block (special modes only).
PAGE 541
256 KByte Flash Module (S12XFTMR256K1V1) Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. Table 18-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 18.4.2.
PAGE 542
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-35. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [22:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 543
256 KByte Flash Module (S12XFTMR256K1V1) phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. Table 18-38. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 18-28) Set if an invalid phrase index is supplied FSTAT FPVIOL 18.4.2.
PAGE 544
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-40. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 18-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 18.4.2.
PAGE 545
256 KByte Flash Module (S12XFTMR256K1V1) R, Table 18-42.
PAGE 546
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-45. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [22:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 18-46.
PAGE 547
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-48.
PAGE 548
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-3). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 18-51.
PAGE 549
256 KByte Flash Module (S12XFTMR256K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. Valid margin level settings for the Set User Margin Level command are defined in Table 18-54. Table 18-54.
PAGE 550
256 KByte Flash Module (S12XFTMR256K1V1) Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. Valid margin level settings for the Set Field Margin Level command are defined in Table 18-57. Table 18-57.
PAGE 551
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-59. Erase Verify D-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x10 Global address [22:16] to identify the D-Flash block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash memory is erased.
PAGE 552
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-61. Program D-Flash Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program D-Flash command launch determines how many words will be programmed in the D-Flash block.
PAGE 553
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-64. Erase D-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 18-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL 18.4.
PAGE 554
256 KByte Flash Module (S12XFTMR256K1V1) Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 18-27. Flash Module Interrupts Implementation 18.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 18.4.3, “Interrupts”). 18.4.
PAGE 555
256 KByte Flash Module (S12XFTMR256K1V1) keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 18-10) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys.
PAGE 556
256 KByte Flash Module (S12XFTMR256K1V1) erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash security byte to the unsecured state and reset the MCU. 18.5.
PAGE 557
Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-1. Revision History Revision Number Revision Date V01.04 03 Jan 2008 V01.05 19 Dec 2008 19.1/19-557 19.4.2.4/19-592 19.4.2.6/19-594 19.4.2.11/19-59 7 19.4.2.11/19-59 7 19.4.2.11/19-59 7 V01.06 25 Sep 2009 The following changes were made to clarify module behavior related to Flash register access during reset sequence and while Flash commands are active: 19.3.2/19-564 - Add caution concerning register writes while command is active 19.3.2.
PAGE 558
128 KByte Flash Module (S12XFTMR128K1V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
PAGE 559
128 KByte Flash Module (S12XFTMR128K1V1) • • • Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Flexible protection scheme to prevent accidental program or erase of P-Flash memory 19.1.2.
PAGE 560
128 KByte Flash Module (S12XFTMR128K1V1) Flash Interface Command Interrupt Request 16bit internal bus Registers Error Interrupt Request P-Flash 16Kx72 sector 0 sector 1 Protection sector 127 Security Oscillator Clock (XTAL) CPU Clock Divider FCLK Memory Controller Scratch RAM 384x16bits D-Flash 4Kx22 sector 0 sector 1 sector 31 Figure 19-1. FTMR128K1 Block Diagram 19.2 External Signal Description The Flash module contains no signals that connect off-chip. 19.
PAGE 561
128 KByte Flash Module (S12XFTMR128K1V1) 19.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x7E_0000 and 0x7F_FFFF as shown in Table 19-2. The P-Flash memory map is shown in Figure 19-2. Table 19-2. P-Flash Memory Addressing Global Address Size (Bytes) 0x7E_0000 – 0x7F_FFFF 128 K Description P-Flash Block 0 Contains Flash Configuration Field (see Table 19-3) The FPROT register, described in Section 19.3.2.
PAGE 562
128 KByte Flash Module (S12XFTMR128K1V1) P-Flash START = 0x7E_0000 Flash Protected/Unprotected Region 96 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 19-2.
PAGE 563
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 19.4.2.6, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 19-5.
PAGE 564
128 KByte Flash Module (S12XFTMR128K1V1) D-Flash START = 0x10_0000 D-Flash Memory 8 Kbytes D-Flash END = 0x10_1FFF 0x12_0000 D-Flash Nonvolatile Information Register (DFIFRON) 128 bytes 0x12_1000 0x12_2000 Memory Controller Scratch RAM (MGRAMON) 768 bytes 0x12_4000 0x12_E800 0x12_FFFF Figure 19-3. D-Flash and Memory Controller Resource Memory Map 19.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013.
PAGE 565
128 KByte Flash Module (S12XFTMR128K1V1) Address & Name 0x0002 FCCOBIX 0x0003 FECCRIX 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 DFPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV0 0x000D FRSV1 0x000E FECCRHI 0x000F FECCRLO R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX2 CCOBIX1 CCOBIX0 ECCRIX2 ECCRIX1 ECCRIX0 FDFD FSFD DFDIE SFDIE MGSTAT1 MGSTAT0 DFDIF SFDIF W R 0 0 0 0 0 W R 0 0 CCIE 0 0 IGNSF W R 0 W R 0 CCIF ACCERR FPVIOL 0 0 MGBUSY
PAGE 566
128 KByte Flash Module (S12XFTMR128K1V1) Address & Name 0x0010 FOPT 0x0011 FRSV2 0x0012 FRSV3 0x0013 FRSV4 R 7 6 5 4 3 2 1 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W = Unimplemented or Reserved Figure 19-4. FTMR128K1 Register Summary (continued) 19.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
PAGE 567
128 KByte Flash Module (S12XFTMR128K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. S12XS Family Reference Manual, Rev. 1.
PAGE 568
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-7. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) 1 2 MIN1 MAX 1.60 2.10 2.40 FDIV[6:0] 2 OSCCLK Frequency (MHz) FDIV[6:0] MIN1 2 MAX 0x01 33.60 34.65 0x20 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.
PAGE 569
128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 19-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 570
128 KByte Flash Module (S12XFTMR128K1V1) 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 19.5. 19.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX[2:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-7.
PAGE 571
128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-9.
PAGE 572
128 KByte Flash Module (S12XFTMR128K1V1) Offset Module Base + 0x0005 7 6 R 5 4 3 2 1 0 DFDIE SFDIE 0 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 19-14.
PAGE 573
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 574
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
PAGE 575
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 19-18 for the P-Flash block.
PAGE 576
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x7F_8000–0x7F_83FF 1 Kbyte 01 0x7F_8000–0x7F_87FF 2 Kbytes 10 0x7F_8000–0x7F_8FFF 4 Kbytes 11 0x7F_8000–0x7F_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 19-14. Although the protection scheme is loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user.
PAGE 577
FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 Scenario 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] FPLS[1:0] FLASH START FPOPEN = 1 128 KByte Flash Module (S12XFTMR128K1V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 19-14.
PAGE 578
128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 19-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 19-21.
PAGE 579
128 KByte Flash Module (S12XFTMR128K1V1) P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the D-Flash memory fully protected. Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the D-Flash memory is not possible if any of the D-Flash sectors are protected. Table 19-22.
PAGE 580
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-23.
PAGE 581
128 KByte Flash Module (S12XFTMR128K1V1) (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 19-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller.
PAGE 582
128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.13 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-19. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 19.3.2.
PAGE 583
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-25. FECCR Index Settings ECCRIX[2:0] 000 FECCR Register Content Bits [15:8] Bit[7] Bits[6:0] Parity bits read from Flash block 0 Global address [22:16] 001 Global address [15:0] 010 Data 0 [15:0] 011 Data 1 [15:0] (P-Flash only) 100 Data 2 [15:0] (P-Flash only) 101 Data 3 [15:0] (P-Flash only) 110 Not used, returns 0x0000 when read 111 Not used, returns 0x0000 when read Table 19-26.
PAGE 584
128 KByte Flash Module (S12XFTMR128K1V1) During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 19-3) as indicated by reset condition F in Figure 19-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. Table 19-27.
PAGE 585
128 KByte Flash Module (S12XFTMR128K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-25. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 19.4 Functional Description 19.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 586
128 KByte Flash Module (S12XFTMR128K1V1) 19.4.1.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 19.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence.
PAGE 587
128 KByte Flash Module (S12XFTMR128K1V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 588
128 KByte Flash Module (S12XFTMR128K1V1) 19.4.1.3 Valid Flash Module Commands Table 19-28. Flash Commands by Mode Unsecured FCMD 1 2 3 4 5 6 7 8 19.4.1.
PAGE 589
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-29. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0 that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and D-Flash) blocks.
PAGE 590
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-30. D-Flash Commands FCMD Command Function on D-Flash Memory 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks and verifying that all D-Flash (and P-Flash) blocks are erased. 0x0D Set User Margin Level Specifies a user margin read level for the D-Flash block. 0x0E Set Field Margin Level Specifies a field margin read level for the D-Flash block (special modes only).
PAGE 591
128 KByte Flash Module (S12XFTMR128K1V1) Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. Table 19-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 19.4.2.
PAGE 592
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-35. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [22:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 593
128 KByte Flash Module (S12XFTMR128K1V1) phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. Table 19-38. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 19-28) Set if an invalid phrase index is supplied FSTAT FPVIOL 19.4.2.
PAGE 594
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-40. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 19-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 19.4.2.
PAGE 595
128 KByte Flash Module (S12XFTMR128K1V1) R, Table 19-42.
PAGE 596
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-45. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [22:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 19-46.
PAGE 597
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-48.
PAGE 598
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-3). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 19-51.
PAGE 599
128 KByte Flash Module (S12XFTMR128K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. Valid margin level settings for the Set User Margin Level command are defined in Table 19-54. Table 19-54.
PAGE 600
128 KByte Flash Module (S12XFTMR128K1V1) Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. Valid margin level settings for the Set Field Margin Level command are defined in Table 19-57. Table 19-57.
PAGE 601
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-59. Erase Verify D-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x10 Global address [22:16] to identify the D-Flash block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash memory is erased.
PAGE 602
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-61. Program D-Flash Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program D-Flash command launch determines how many words will be programmed in the D-Flash block.
PAGE 603
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-64. Erase D-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 19-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL 19.4.
PAGE 604
128 KByte Flash Module (S12XFTMR128K1V1) Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 19-27. Flash Module Interrupts Implementation 19.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 19.4.3, “Interrupts”). 19.4.
PAGE 605
128 KByte Flash Module (S12XFTMR128K1V1) keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 19-10) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys.
PAGE 606
128 KByte Flash Module (S12XFTMR128K1V1) erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash security byte to the unsecured state and reset the MCU. 19.5.
PAGE 607
Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-1. Revision History Revision Number Revision Date V01.04 03 Jan 2008 V01.05 19 Dec 2008 20.1/20-607 20.4.2.4/20-642 20.4.2.6/20-644 20.4.2.11/20-64 8 20.4.2.11/20-64 8 20.4.2.11/20-64 8 V01.06 25 Sep 2009 The following changes were made to clarify module behavior related to Flash register access during reset sequence and while Flash commands are active: 20.3.2/20-615 - Add caution concerning register writes while command is active 20.3.2.
PAGE 608
64 KByte Flash Module (S12XFTMR64K1V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
PAGE 609
64 KByte Flash Module (S12XFTMR64K1V1) • • • Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Flexible protection scheme to prevent accidental program or erase of P-Flash memory 20.1.2.
PAGE 610
64 KByte Flash Module (S12XFTMR64K1V1) 20.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 20-1. Figure 20-1. FTMR64K1 Block Diagram Flash Interface Command Interrupt Request 16bit internal bus Registers Error Interrupt Request P-Flash 8Kx72 sector 0 sector 1 Protection sector 63 Security Oscillator Clock (XTAL) CPU Clock Divider FCLK Memory Controller Scratch RAM 384x16bits D-Flash 2Kx22 sector 0 sector 1 sector 15 20.
PAGE 611
64 KByte Flash Module (S12XFTMR64K1V1) 20.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 20.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x7F_0000 and 0x7F_FFFF as shown in Table 20-2.
PAGE 612
64 KByte Flash Module (S12XFTMR64K1V1) 2 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF. S12XS Family Reference Manual, Rev. 1.
PAGE 613
64 KByte Flash Module (S12XFTMR64K1V1) P-Flash START = 0x7F_0000 Flash Protected/Unprotected Region 32 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 20-2.
PAGE 614
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 20.4.2.6, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 20-5.
PAGE 615
64 KByte Flash Module (S12XFTMR64K1V1) D-Flash START = 0x10_0000 D-Flash Memory 4 Kbytes D-Flash END = 0x10_0FFF 0x12_0000 D-Flash Nonvolatile Information Register (DFIFRON) 128 bytes 0x12_1000 0x12_2000 Memory Controller Scratch RAM (MGRAMON) 768 bytes 0x12_4000 0x12_E800 0x12_FFFF Figure 20-3. D-Flash and Memory Controller Resource Memory Map 20.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013.
PAGE 616
64 KByte Flash Module (S12XFTMR64K1V1) Address & Name 0x0002 FCCOBIX 0x0003 FECCRIX 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 DFPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV0 0x000D FRSV1 0x000E FECCRHI 0x000F FECCRLO R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX2 CCOBIX1 CCOBIX0 ECCRIX2 ECCRIX1 ECCRIX0 FDFD FSFD DFDIE SFDIE MGSTAT1 MGSTAT0 DFDIF SFDIF W R 0 0 0 0 0 W R 0 0 CCIE 0 0 IGNSF W R 0 W R 0 CCIF ACCERR FPVIOL 0 0 MGBUSY RS
PAGE 617
64 KByte Flash Module (S12XFTMR64K1V1) Address & Name 0x0010 FOPT 0x0011 FRSV2 0x0012 FRSV3 0x0013 FRSV4 R 7 6 5 4 3 2 1 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W = Unimplemented or Reserved Figure 20-4. FTMR64K1 Register Summary (continued) 20.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
PAGE 618
64 KByte Flash Module (S12XFTMR64K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. S12XS Family Reference Manual, Rev. 1.
PAGE 619
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-7. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) 1 2 MIN1 MAX 1.60 2.10 2.40 FDIV[6:0] 2 OSCCLK Frequency (MHz) FDIV[6:0] MIN1 2 MAX 0x01 33.60 34.65 0x20 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.
PAGE 620
64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 20-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 621
64 KByte Flash Module (S12XFTMR64K1V1) 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 20.5. 20.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX[2:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-7.
PAGE 622
64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-9.
PAGE 623
64 KByte Flash Module (S12XFTMR64K1V1) Offset Module Base + 0x0005 7 6 R 5 4 3 2 1 0 DFDIE SFDIE 0 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 20-14.
PAGE 624
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 625
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
PAGE 626
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 20-18 for the P-Flash block.
PAGE 627
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x7F_8000–0x7F_83FF 1 Kbyte 01 0x7F_8000–0x7F_87FF 2 Kbytes 10 0x7F_8000–0x7F_8FFF 4 Kbytes 11 0x7F_8000–0x7F_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 20-14. Although the protection scheme is loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user.
PAGE 628
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 64 KByte Flash Module (S12XFTMR64K1V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 20-14.
PAGE 629
64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 20-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 20-21.
PAGE 630
64 KByte Flash Module (S12XFTMR64K1V1) P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the D-Flash memory fully protected. Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the D-Flash memory is not possible if any of the D-Flash sectors are protected. Table 20-22.
PAGE 631
64 KByte Flash Module (S12XFTMR64K1V1) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 20-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 20-17. Flash Common Command Object Low Register (FCCOBLO) 20.3.2.11.
PAGE 632
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 20.3.2.12 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing.
PAGE 633
64 KByte Flash Module (S12XFTMR64K1V1) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault. Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 20-20.
PAGE 634
64 KByte Flash Module (S12XFTMR64K1V1) The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four data words and the parity byte are the uncorrected data read from the P-Flash block. The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The uncorrected 16-bit data word is addressed by ECCRIX = 010. 20.3.2.
PAGE 635
64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.17 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 20-24. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 20.3.2.18 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 636
64 KByte Flash Module (S12XFTMR64K1V1) 20.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 20-7 shows recommended values for the FDIV field based on OSCCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash memory due to overstress.
PAGE 637
64 KByte Flash Module (S12XFTMR64K1V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 638
64 KByte Flash Module (S12XFTMR64K1V1) 20.4.1.3 Valid Flash Module Commands Table 20-28. Flash Commands by Mode Unsecured FCMD 1 2 3 4 5 6 7 8 20.4.1.
PAGE 639
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-29. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0 that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and D-Flash) blocks.
PAGE 640
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-30. D-Flash Commands FCMD Command Function on D-Flash Memory 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks and verifying that all D-Flash (and P-Flash) blocks are erased. 0x0D Set User Margin Level Specifies a user margin read level for the D-Flash block. 0x0E Set Field Margin Level Specifies a field margin read level for the D-Flash block (special modes only).
PAGE 641
64 KByte Flash Module (S12XFTMR64K1V1) Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. Table 20-32.
PAGE 642
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-35. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [22:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 643
64 KByte Flash Module (S12XFTMR64K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. Table 20-38.
PAGE 644
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-40.
PAGE 645
64 KByte Flash Module (S12XFTMR64K1V1) R, Table 20-42.
PAGE 646
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-45. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [22:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 20-46.
PAGE 647
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-48.
PAGE 648
64 KByte Flash Module (S12XFTMR64K1V1) 20.4.2.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 20-9). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 20-3).
PAGE 649
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-53. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0D 001 Global address [22:16] to identify the Flash block Margin level setting Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. Valid margin level settings for the Set User Margin Level command are defined in Table 20-54. Table 20-54.
PAGE 650
64 KByte Flash Module (S12XFTMR64K1V1) 20.4.2.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of a specific P-Flash or D-Flash block. Table 20-56.
PAGE 651
64 KByte Flash Module (S12XFTMR64K1V1) NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 20.4.2.14 Erase Verify D-Flash Section Command The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased.
PAGE 652
64 KByte Flash Module (S12XFTMR64K1V1) CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 20-61.
PAGE 653
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-63. Erase D-Flash Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 001 Global address [15:0] anywhere within the sector to be erased. See Section 20.1.2.2 for D-Flash sector size. Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase D-Flash Sector operation has completed. Table 20-64.
PAGE 654
64 KByte Flash Module (S12XFTMR64K1V1) the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 20.3.2.5, “Flash Configuration Register (FCNFG)”, Section 20.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 20.3.2.7, “Flash Status Register (FSTAT)”, and Section 20.3.2.8, “Flash Error Status Register (FERSTAT)”.
PAGE 655
64 KByte Flash Module (S12XFTMR64K1V1) 20.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 20.3.2.2), the Verify Backdoor Access Key command (see Section 20.4.2.
PAGE 656
64 KByte Flash Module (S12XFTMR64K1V1) • Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash memory and run code from external memory to execute the Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode.
PAGE 657
Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. Data are currently based on characterization data of 9S12XS128 material only unless marked differently. This supplement contains the most accurate electrical information for the S12XS family microcontroller available at the time of publication.
PAGE 658
Electrical Characteristics The VDDX, VSSX pin pairs [2:1] supply the I/O pins. VDDR supplies the internal voltage regulator. VDDPLL, VSSPLL pin pair supply the oscillator and the PLL. VSS1, VSS2 and VSS3 are internally connected by metal. All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal. VDDA is connected to all VDDX pins by diodes for ESD protection such that VDDX must not exceed VDDA by more than a diode voltage drop.
PAGE 659
Electrical Characteristics A.1.3.4 TEST This pin is used for production testing only. The TEST pin must be tied to VSS in all applications. A.1.4 Current Injection Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD35) is greater than IDD35, the injection current may flow out of VDD35 and could result in external power supply going out of regulation.
PAGE 660
Electrical Characteristics Table A-1. Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit VDD35 –0.3 6.0 V VDD –0.3 2.16 V 1 I/O, regulator and analog supply voltage 2 Digital logic supply voltage2 3 PLL supply voltage2 VDDPLL –0.3 2.16 V 4 NVM supply voltage2 VDDF –0.3 3.6 V 5 Voltage difference VDDX to VDDA ∆VDDX –6.0 0.3 V 6 Voltage difference VSSX to VSSA ∆VSSX –0.3 0.3 V 7 Digital I/O input voltage VIN –0.3 6.0 V 8 Analog reference VRH, VRL –0.
PAGE 661
Electrical Characteristics Table A-2. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series resistance R1 1500 Ohm Storage capacitance C 100 pF Number of pulse per pin Positive Negative — — 1 1 Charged Device Number of pulse per pin Positive Negative — — 3 3 Latch-up Minimum input voltage limit — –2.5 V Maximum input voltage limit — 7.5 V Human Body Table A-3. ESD and Latch-Up Protection Characteristics Num C 1 C 2 3 4 A.1.
PAGE 662
Electrical Characteristics Table A-4. Operating Conditions Voltage difference VDDR to VDDX ∆VDDR Voltage difference VSSX to VSSA ∆VSSX Voltage difference VSS1 , VSS2 , VSS3 , VSSPLL to VSSX ∆VSS -0.1 0 0.1 V Digital logic supply voltage1 VDD 1.72 1.8 1.98 V PLL supply voltage VDDPLL 1.72 1.8 1.98 V 2 Oscillator (Loop Controlled Pierce) (Full Swing Pierce) fosc 4 2 — — 16 40 MHz Bus frequency3 fbus 0.
PAGE 663
Electrical Characteristics The total power dissipation can be calculated from: P P D = P INT +P IO = Chip Internal Power Dissipation, [W] 2 P = R ⋅I IO DSON IO i i INT ∑ PIO is the sum of all output currents on I/O ports associated with VDDX, whereby R R V OL = ------------ ;for outputs driven low DSON I OL V –V DD35 OH = -------------------------------------- ;for outputs driven high DSON I OH Two cases with internal voltage regulator enabled and disabled must be considered: 1.
PAGE 664
Electrical Characteristics Table A-5.
PAGE 665
Electrical Characteristics Table A-6.
PAGE 666
Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Table A-7. 3.3-V I/O Characteristics Conditions are 3.13 V < VDD35 < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Symbol Min Typ Max Unit P Input high voltage VIH 0.65*VDD35 — — V T Input high voltage VIH — — VDD35 + 0.
PAGE 667
Electrical Characteristics Table A-7. 3.3-V I/O Characteristics Conditions are 3.13 V < VDD35 < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins.
PAGE 668
Electrical Characteristics Table A-8. 5-V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C 1 Rating Symbol Min Typ Max Unit 0.65*VDD35 — — V P Input high voltage V T Input high voltage VIH — — VDD35 + 0.3 V P Input low voltage VIL — — 0.35*VDD35 V T Input low voltage VIL VSS35 – 0.
PAGE 669
Electrical Characteristics Table A-8. 5-V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. 16 D Port H, J, P interrupt input pulse passed (STOP) tPULSE 4 — — tcyc 17 D IRQ pulse width, edge-sensitive mode (STOP) PWIRQ 1 — — tcyc PWXIRQ 18 D XIRQ pulse width with X-bit set (STOP) Maximum leakage current occurs at maximum operating temperature.
PAGE 670
Electrical Characteristics 4MHz loop controlled Pierce oscillator. Production test parameters are tested with a 4MHz square wave oscillator. Table A-10 shows the configuration of the peripherals for maximum run current Table A-10. Module Configurations for Maximum Run Supply (VDDR+VDDA) Current VDD35=5.
PAGE 671
Electrical Characteristics Table A-12. Run and Wait Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit Run supply current (No external load, Peripheral Configuration see Table A-10.) 1 1a P P Peripheral Set1 fosc=4MHz, fbus=40MHz IDD35 Peripheral Set1 Device 9S12XS256 fosc=4MHz, fbus=40MHz IDD35 mA — — 32 — — 35 mA Run supply current (No external load, Peripheral Configuration see Table A-9.
PAGE 672
Electrical Characteristics Table A-13.
PAGE 673
Electrical Characteristics A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics The Table A-14 and Table A-15 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to.
PAGE 674
Electrical Characteristics is recommended to configure PortAD pins as outputs only for low frequency, low load outputs. The impact on ATD accuracy is load dependent and not specified. The values specified are valid under condition that no PortAD output drivers switch during conversion. A.2.2.2 Source Resistance Due to the input pin leakage current as specified in Table A-7 and Table A-8 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input.
PAGE 675
Electrical Characteristics Table A-15. ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit RS — — 1 KΩ 1 C Max input source resistance1 2 D Total input capacitance Non sampling Total input capacitance Sampling CINN CINS — — — — 10 16 pF 3 D Input internal Resistance RINA — 5 15 kΩ 4 C Disruptive analog input current INA –2.5 — 2.
PAGE 676
Electrical Characteristics A.2.3.1 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = --------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ V –V n 0 DNL ( i ) = --------------------- – n 1LSB i=1 S12XS Family Reference Manual, Rev. 1.
PAGE 677
Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $FF $3FC $3FB $3FA $3F9 $FE $3F8 $3F7 $3F6 $3F5 10-Bit Resolution $3F3 9 Ideal Transfer Curve 2 8 8-Bit Resolution $FD $3F4 7 10-Bit Transfer Curve 6 5 1 4 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 55 60 65 70 75 80 85 90 95 100 105 110 115 120 5000 + Vin mV Figure A-1.
PAGE 678
Electrical Characteristics Table A-16. ATD Conversion Performance 5V range Conditions are shown in Table A-4. unless otherwise noted. VREF = VRH - VRL = 5.12V. fATDCLK = 8.0MHz The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions. Rating1,2 Num C Symbol Min Typ Max Unit 1 P Resolution 12-Bit LSB — 1.25 — mV 2 P Differential Nonlinearity 12-Bit DNL -4 ±2 4 counts 3 P Integral Nonlinearity 12-Bit INL -5 ±2.
PAGE 679
Electrical Characteristics A.3 NVM, Flash A.3.1 Timing Parameters The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum.
PAGE 680
Electrical Characteristics A.3.1.4 Read Once (FCMD=0x04) The maximum read once time is given by 1 t = ( 400 ) ⋅ --------------------f NVMBUS A.3.1.5 Program P-Flash (FCMD=0x06) The programming time for a single phrase of four P-Flash words + associated eight ECC bits is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formulas.
PAGE 681
Electrical Characteristics A.3.1.8 Erase P-Flash Block (FCMD=0x09) Erasing a 256K NVM block takes 1 1 t mass ≈ 100100 ⋅ ------------------------- + 70000 ⋅ ---------------------------f NVMBUS f NVMOP Erasing a 128K NVM block takes 1 1 t mass ≈ 100100 ⋅ ------------------------- + 35000 ⋅ ---------------------------f NVMBUS f NVMOP A.3.1.
PAGE 682
Electrical Characteristics 1 t = 350 ⋅ ---------------------------f NVMBUS A.3.1.14 Erase Verify D-Flash Section (FCMD=0x10) Erase Verify D-Flash for a given number of words NW is given by . 1 t check ≈ ( 840 + N W ) ⋅ ---------------------------f NVMBUS A.3.1.15 D-Flash Programming (FCMD=0x11) D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, because programming across a row boundary requires extra steps.
PAGE 683
Electrical Characteristics Table A-18. NVM Timing Characteristics Conditions are as shown in Table A-4, with 40MHz bus and fNVMOP= 1MHz unless otherwise noted.
PAGE 684
Electrical Characteristics Table A-19.
PAGE 685
Electrical Characteristics A.4 Voltage Regulator Table A-20. Voltage Regulator Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Input Voltages 2 P 3 4 1 2 3 4 5 Characteristic Symbol Min Typical Max Unit VVDDR,A 3.13 — 5.50 V Output Voltage Core Full Performance Mode Reduced Power Mode (MCU STOP mode) VDD 1.72 — 1.84 1.60 1.98 — V V P Output Voltage Flash Full Performance Mode Reduced Power Mode (MCU STOP mode) VDDF 2.60 — 2.
PAGE 686
Electrical Characteristics A.5 Output Loads A.5.1 Resistive Loads The voltage regulator is intended to supply the internal logic and oscillator. It allows no external DC loads. A.5.2 Capacitive Loads The capacitive loads are specified in Table A-21. Ceramic capacitors with X7R dielectricum are required. Table A-21.
PAGE 687
Electrical Characteristics V VDDR, VDDX VDDA >= 0 t Figure A-3. S12XS family Power Sequencing During power sequencing VDDA can be powered up before VDDR, VDDX. VDDR and VDDX must be powered up together adhering to the operating conditions differential. VRH power up must follow VDDA to avoid current injection. S12XS Family Reference Manual, Rev. 1.
PAGE 688
Electrical Characteristics A.6 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (PLL). A.6.1 Startup Table A-22 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) block description Table A-22.
PAGE 689
Electrical Characteristics A.6.1.5 Pseudo Stop and Wait Recovery The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector. S12XS Family Reference Manual, Rev. 1.
PAGE 690
Electrical Characteristics A.6.2 Oscillator Table A-23. Oscillator Characteristics Conditions are shown in Table A-4. unless otherwise noted Num C Symbol Min Typ Max Unit 1a C Crystal oscillator range (loop controlled Pierce) fOSC 4.0 — 16 MHz 1b C Crystal oscillator range (full swing Pierce) 1,2 fOSC 2.0 — 40 MHz 2 P Startup Current iOSC 100 — — µA 3a C Oscillator start-up time (LCP, 4MHz)3 tUPOSC — 2.2 10 ms 3b C Oscillator start-up time (LCP, 8MHz)3 tUPOSC — 1.
PAGE 691
Electrical Characteristics A.6.3 Phase Locked Loop A.6.3.1 Jitter Information With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter.
PAGE 692
Electrical Characteristics For N < 1000, the following equation is a good fit for the maximum jitter: j1 J ( N ) = -------- + j 2 N J(N) 1 5 10 20 N Figure A-5. Maximum bus clock jitter approximation NOTE On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent. Table A-24.
PAGE 693
Electrical Characteristics A.7 MSCAN Table A-25. MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN wakeup dominant pulse filtered tWUP — — 1.5 µs 2 P MSCAN wakeup dominant pulse pass tWUP 5 — — µs S12XS Family Reference Manual, Rev. 1.
PAGE 694
Electrical Characteristics A.8 SPI Timing This section provides electrical parametrics and ratings for the SPI. In Table A-26 the measurement conditions are listed. Table A-26. Measurement Conditions Description Drive mode Load capacitance CLOAD1, on all outputs Thresholds for delay measurement points 1 Timing specified for equal load on all SPI output pins. Avoid asymmetric load. A.8.
PAGE 695
Electrical Characteristics In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS (Output) 1 2 12 13 3 12 13 SCK (CPOL = 0) (Output) 4 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 6 MSB IN2 Port Data LSB IN 11 9 MOSI (Output) Bit MSB-1. . . 1 Master MSB OUT2 Bit MSB-1. . . 1 Master LSB OUT Port Data 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. Figure A-7.
PAGE 696
Electrical Characteristics fSCK/fbus 1/2 1/4 5 15 10 25 20 35 30 fbus [MHz] 40 Figure A-8. Derating of maximum fSCK to fbus ratio in Master Mode A.8.2 Slave Mode In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. SS (Input) 1 12 13 3 12 13 SCK (CPOL = 0) (Input) 4 2 4 SCK (CPOL = 1) (Input) 10 8 7 MISO (Output) 9 See Note Slave MSB 5 MOSI (Input) Bit MSB-1 . . . 1 11 11 Slave LSB OUT See Note 6 MSB IN Bit MSB-1. . .
PAGE 697
Electrical Characteristics In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. SS (Input) 3 1 2 12 13 12 13 SCK (CPOL = 0) (Input) 4 4 SCK (CPOL = 1) (Input) See Note 7 Slave MSB OUT 5 MOSI (Input) 8 11 9 MISO (Output) Bit MSB-1 . . . 1 Slave LSB OUT 6 MSB IN Bit MSB-1 . . . 1 LSB IN NOTE: Not defined Figure A-10. SPI Slave Timing (CPHA = 1) In Table A-28 the timing characteristics for slave mode are listed. Table A-28.
PAGE 698
Package Information Appendix B Package Information This section provides the physical dimensions of the S12XS family packages. S12XS Family Reference Manual, Rev. 1.
PAGE 699
Package Information B.1 112-pin LQFP Mechanical Dimensions Figure B-1. 112-pin LQFP (case no. 987) - page 1 S12XS Family Reference Manual, Rev. 1.
PAGE 700
Package Information Figure B-2. 112-pin LQFP (case no. 987) - page 2 S12XS Family Reference Manual, Rev. 1.
PAGE 701
Package Information Figure B-3. 112-pin LQFP (case no. 987) - page 3 S12XS Family Reference Manual, Rev. 1.
PAGE 702
Package Information B.2 80-Pin QFP Mechanical Dimensions Figure B-4. 80-pin QFP (case no. 841B) - page 1 S12XS Family Reference Manual, Rev. 1.
PAGE 703
Package Information Figure B-5. 80-pin QFP (case no. 841B) - page 2 S12XS Family Reference Manual, Rev. 1.
PAGE 704
Package Information Figure B-6. 80-pin QFP (case no. 841B) - page 3 S12XS Family Reference Manual, Rev. 1.
PAGE 705
Package Information B.3 64-Pin LQFP Mechanical Dimensions S12XS Family Reference Manual, Rev. 1.
PAGE 706
Package Information Figure B-7. 64-pin LQFP (case no. 840F) - page 2 S12XS Family Reference Manual, Rev. 1.
PAGE 707
Package Information Figure B-8. 64-pin LQFP (case no. 840F) - page 3 S12XS Family Reference Manual, Rev. 1.
PAGE 708
PCB Layout Guidelines Appendix C PCB Layout Guidelines C.1 General The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins . • Central point of the ground star should be the VSS3 pin. • Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
PAGE 709
PCB Layout Guidelines C.1.1 112-Pin LQFP Recommended PCB Layout Figure C-1. 112-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) S12XS Family Reference Manual, Rev. 1.
PAGE 710
PCB Layout Guidelines C.1.2 80-Pin QFP Recommended PCB Layout Figure C-2. 80-Pin QFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) S12XS Family Reference Manual, Rev. 1.
PAGE 711
PCB Layout Guidelines C.1.3 64-Pin LQFP Recommended PCB Layout TBD Figure C-3. 64-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) S12XS Family Reference Manual, Rev. 1.
PAGE 712
Derivative Differences Appendix D Derivative Differences D.1 Memory Sizes and Package Options S12XS family Table D-1. Package and Memory Options of S12XS family Device Package Flash RAM Data Flash 9S12XS256 112 LQFP 256K 12K 8K 128K 8K 8K 64K 4K 4K 80 QFP 64 LQFP 9S12XS128 112 LQFP 80 QFP 64 LQFP 9S12XS64 112 LQFP 80 QFP 64 LQFP Table D-2.
PAGE 713
Detailed Register Address Map Appendix E Detailed Register Address Map E.1 Detailed Register Map The following tables show the detailed register map of the S12XS family.
PAGE 714
Detailed Register Address Map 0x000E–0x000F Reserved Register Space Address Name 0x000E Reserved 0x000F Reserved R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 2 Address Name 0x0010 GPAGE 0x0011 DIRECT 0x0012 Reserved 0x0013 MMCCTL1 0x0014 Reserved 0x0015 PPAGE 0x0016 RPAGE 0x0017 EPAGE Bit 7 R 0 W R DP15 W R 0 W R MGRAMO N W R 0 W R PIX7 W R RP7 W R EP7 W Bit 6
PAGE 715
Detailed Register Address Map 0x001E–0x001F Port Integration Module (PIM) Map 3 of 5 Address Name 0x001E IRQCR 0x001F Reserved R W R W Bit 7 Bit 6 IRQE IRQEN 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020–0x002F Debug Module (S12XDBG) Map Address Name Bit 7 Bit 6 Bit 5 R 0 0x0020 DBGC1 ARM reserved BDM DBGBRK reserved W TRIG R TBF 0 0 0 0 SSF2 0x0021 DBGSR W R 0x0022 DBGTCR reserved TSOURCE TRANGE TRCMOD W R 0 0
PAGE 716
Detailed Register Address Map 0x0030–0x0031 Reserved Register Space Address Name 0x0030 Reserved 0x0031 Reserved R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5 Address Name 0x0032 PORTK 0x0033 DDRK Bit 7 R W R W PK7 DDRK7 Bit 6 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PK5 PK4 PK3 PK2 PK1 PK0 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 Bit 3 Bit 2 Bit 1 Bit 0 0
PAGE 717
Detailed Register Address Map 0x0040–0x006F Timer Module (TIM) Map Address Name 0x0040 TIOS 0x0041 CFORC 0x0042 OC7M 0x0043 OC7D 0x0044 TCNTH 0x0045 TCNTL 0x0046 TSCR1 0x0047 TTOV 0x0048 TCTL1 0x0049 TCTL2 0x004A TCTL3 0x004B TCTL4 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 TC0H 0x0051 TC0L 0x0052 TC1H 0x0053 TC1L 0x0054 TC2H 0x0055 TC2L 0x0056 TC3H R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit
PAGE 718
Detailed Register Address Map 0x0040–0x006F Timer Module (TIM) Map Address Name 0x0057 TC3L 0x0058 TC4H 0x0059 TC4L 0x005A TC5H 0x005B TC5L 0x005C TC6H 0x005D TC6L 0x005E TC7H 0x005F TC7L 0x0060 PACTL 0x0061 PAFLG 0x0062 PACNTH 0x0063 PACNTL 0x0064– 0x006B Reserved 0x006C OCPD 0x006D Reserved 0x006E PTPSR 0x006F Reserved Bit 7 R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R 0 W R 0 W R PACNT15 W R PACNT7 W R 0 W R OCPD7 W
PAGE 719
Detailed Register Address Map 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R IREN TNP1 TNP0 SBR12 SBR11 W R SBR7 SBR6 SBR5 SBR4 SBR3 0x00C9 SCI0BDL1 W R LOOPS SCISWAI RSRC M WAKE 0x00CA SCI0CR11 W R 0 0 0 0 RXEDGIF 0x00C8 SCI0ASR12 W R 0 0 0 0 RXEDGIE 0x00C9 SCI0ACR12 W R 0 0 0 0 0 0x00CA SCI0ACR22 W R 0x00CB SCI0CR2 TIE TCIE RIE ILIE TE W R TDRE TC RDRF IDLE OR 0x00CC SCI0SR1 W R 0 0 0x00CD SCI0SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x00CE SCI0DRH T8
PAGE 720
Detailed Register Address Map 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R 0 0 AMAP TXPOL RXPOL W R R8 0 0 0 0x00D6 SCI1DRH T8 W R R7 R6 R5 R4 R3 0x00D7 SCI1DRL W T7 T6 T5 T4 T3 1 Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero 2 Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one 0x00D5 SCI1SR2 Bit 2 Bit 1 Bit 0 BRK13 TXDIR 0 0 0 R2 T2 R1 T1 R0 T0 RA
PAGE 721
Detailed Register Address Map 0x0100–0x0113 NVM Control Register (FTMR) Map (continued) Address Name 0x0104 FCNFG 0x0105 FERCNFG 0x0106 FSTAT 0x0107 FERSTAT 0x0108 FPROT 0x0109 DFPROT 0x010A FCCOBHI 0x010B FCCOBLO 0x010C Reserved 0x010D Reserved 0x010E FECCRHI 0x010F FECCRLO 0x0110 FOPT 0x0111 Reserved 0x0112 Reserved 0x0113 Reserved Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CCIE 0 CCIF 0 FPOPEN Bit 6 Bit 5 0 0 0 0 0 ACCERR FPVIOL 0
PAGE 722
Detailed Register Address Map 0x0120–0x012F Interrupt Module (S12XINT) Map Address Name 0x0120 Reserved 0x0121 IVBR 0x0122 Reserved 0x0123 Reserved 0x0124 Reserved 0x0125 Reserved 0x0126 INT_XGPRIO 0x0127 INT_CFADDR 0x0128 INT_CFDATA0 0x0129 INT_CFDATA1 0x012A INT_CFDATA2 0x012B INT_CFDATA3 0x012C INT_CFDATA4 0x012D INT_CFDATA5 0x012E INT_CFDATA6 0x012F INT_CFDATA7 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0
PAGE 723
Detailed Register Address Map 0x0140–0x017F MSCAN (CAN0) Map (continued) Address Name 0x0142 CAN0BTR0 0x0143 CAN0BTR1 0x0144 CAN0RFLG 0x0145 CAN0RIER 0x0146 CAN0TFLG 0x0147 CAN0TIER 0x0148 CAN0TARQ 0x0149 CAN0TAAK 0x014A CAN0TBSEL 0x014B CAN0IDAC 0x014C Reserved 0x014D CAN0MISC 0x014E CAN0RXERR 0x014F CAN0TXERR 0x01500x0153 CAN0IDAR0CAN0IDAR3 0x0154- CAN0IDMR00x0157 CAN0IDMR3 0x01580x015B CAN0IDAR4CAN0IDAR7 0x015C- CAN0IDMR40x015F CAN0IDMR7 0x01600x016F CAN0RXFG 0x01700x
PAGE 724
Detailed Register Address Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address 0xXXX0 0xXXX1 0xXXX2 0xXXX3 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 0xXXX4- CANxRDSR00xXXXB CANxRDSR7 0xXXXC CANRxDLR 0xXXXD Reserved 0xXXXE CANxRTSRH 0xXXXF 0xXX10 0xXX0x XX10 0xXX12 0xXX13 CANxRTSRL Extended ID CANxTIDR0 Standard ID Extended ID CANxTIDR1 Standard ID Extended ID CANxTIDR2 Standa
PAGE 725
Detailed Register Address Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name 0xXX1F CANxTTSRL R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 0x0180–0x023F Reserved Register Space Address Name 0x01800x023F Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name 0x0240 PTT 0x0241 PTIT 0x0242
PAGE 726
Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 MODRR 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R
PAGE 727
Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name 0x0260 PTH 0x0261 PTIH 0x0262 DDRH 0x0263 RDRH 0x0264 PERH 0x0265 PPSH 0x0266 PIEH 0x0267 PIFH 0x0268 PTJ 0x0269 PTIJ 0x026A DDRJ 0x026B RDRJ 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026f PIFJ 0x0270 PT0AD0 0x0271 PT1AD0 0x0272 DDR0AD0 0x0273 DDR1AD0 0x0274 RDR0AD0 0x0275 RDR1AD0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
PAGE 728
Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name 0x0276 PER0AD0 0x0277 PER1AD0 0x02780x027F Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 7 6 5 4 3 2 1 0 W R PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 7 6 5 4 3 2 1 0 W R 0 0 0 0 0 0 0 0 W 0x0280–0x02BF Reserved Register Space Address Name 0x02800x02BF Reserved R W Bit 7 Bit 6 Bit 5 Bit 4
PAGE 729
Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map (continued) Address Name R CMPHT7 W R Bit15 ATD0DR0H W R Bit7 ATD0DR0L W R Bit15 ATD0DR1H W R Bit7 ATD0DR1L W R Bit15 ATD0DR2H W R Bit7 ATD0DR2L W R Bit15 ATD0DR3H W R Bit7 ATD0DR3L W R Bit15 ATD0DR4H W R Bit7 ATD0DR4L W R Bit15 ATD0DR5H W R Bit7 ATD0DR5L W R Bit15 ATD0DR6H W R Bit7 ATD0DR6L W R Bit15 ATD0DR7H W R Bit7 ATD0DR7L W R Bit15 ATD0DR8H W R Bit7 ATD0DR8L W R Bit15 ATD0DR9H W R Bit7 ATD0DR9L W R
PAGE 730
Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map (continued) Address Name 0x02E6 ATD0DR11H 0x02E7 ATD0DR11L 0x02E8 ATD0DR12H 0x02E9 ATD0DR12L 0x02EA ATD0DR13H 0x02EB ATD0DR13L 0x02EC ATD0DR14H 0x02ED ATD0DR14L 0x02EE ATD0DR15H 0x02EF ATD0DR15L R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9
PAGE 731
Detailed Register Address Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 0x0314 0x0315 0x0316 Name Bit 7 R PWME7 W R PWMPOL PPOL7 W R PWMCLK PCLK7 W R 0 PWMPRCLK W R PWMCAE CAE7 W R PWMCTL CON67 W R 0 PWMTST Test Only W R 0 PWMPRSC W R PWMSCLA Bit 7 W R PWMSCLB Bit 7 W R 0 PWMSCNTA W R 0 PWMSCNTB W R Bit 7 PWMCNT0 W 0 R Bit 7 PWMCNT1 W 0 R
PAGE 732
Detailed Register Address Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address Name 0x0317 PWMPER3 0x0318 PWMPER4 0x0319 PWMPER5 0x031A PWMPER6 0x031B PWMPER7 0x031C PWMDTY0 0x031D PWMDTY1 0x031E PWMDTY2 0x031F PWMDTY3 0x0320 PWMDTY4 0x0321 PWMDTY5 0x0322 PWMDTY6 0x0323 PWMDTY7 0x0324 PWMSDN 0x0325 Reserved 0x0326 Reserved 0x0327 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi
PAGE 733
Detailed Register Address Map 0x00340–0x0367 – Periodic Interrupt Timer (PIT) Map Address Name 0x0340 PITCFLMT 0x0341 PITFLT 0x0342 PITCE 0x0343 PITMUX 0x0344 PITINTE 0x0345 PITTF 0x0346 PITMTLD0 0x0347 PITMTLD1 0x0348 PITLD0 (hi) 0x0349 PITLD0 (lo) 0x034A PITCNT0 (hi) 0x034B PITCNT0 (lo) 0x034C PITLD1 (hi) 0x034D PITLD1 (lo) 0x034E PITCNT1 (hi) 0x034F PITCNT1 (lo) 0x0350 PITLD2 (hi) 0x0351 PITLD2 (lo) 0x0352 PITCNT2 (hi) 0x0353 PITCNT2 (lo) 0x0354 PITLD3 (hi) 0x
PAGE 734
Detailed Register Address Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R PCNT15 W R 0x0357 PITCNT3 (lo) PCNT7 W R 0 0x0358– Reserved 0x0367 W 0x0356 PITCNT3 (hi) 0x0368–0x077F Reserved Address 0x0368 Name Reserved R W S12XS Family Reference Manual, Rev. 1.
PAGE 735
Ordering Information Appendix F Ordering Information F.1 Ordering Information The following figure provides an ordering part number example for the devices covered by this data book. There are two options when ordering a device. Customers must choose between ordering either the maskspecific part number or the generic / mask-independent part number.
PAGE 736
Ordering Information S12XS Family Reference Manual, Rev. 1.
PAGE 737
PAGE 738
How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 or 480-768-2130 Europe, Middle East, and Africa: +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) Japan: Freescale Semiconductor Japan Ltd.