Datasheet

S12X Debug (S12XDBGV3) Module
S12XS Family Reference Manual Rev. 1.13
Freescale Semiconductor 209
The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.4 Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further triggers on the same channel have no affect.
6.3.2.8 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
0010 Any match triggers to Final State
0011 Match0 triggers to State1....... Other matches have no effect
0100 Match0 triggers to State2....... Other matches have no effect
0101 Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect
0110 Match1 triggers to State1....... Other matches have no effect
0111 Match1 triggers to State2....... Other matches have no effect
1000 Match1 triggers to Final State....... Other matches have no effect
1001 Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect
1010 Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
1011 Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect
1100 Match2 triggers to Final State....... Other matches have no effect
1101 Match3 triggers to Final State....... Other matches have no effect
1110 Reserved. (No match triggers state sequencer transition)
1111 Reserved. (No match triggers state sequencer transition)
Address: 0x0027
76543210
R0000MC3MC2MC1MC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-12. Debug Match Flag Register (DBGMFR)
Table 6-24. State3 — Sequencer Next State Selection
SC[3:0] Description