Datasheet

MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor34
2.11.1 Control Timing
Figure 11. Reset Timing
Figure 12. IRQ/KBIPx Timing
Table 17. Control Timing
Num C Parameter Symbol Min Typical
1
1
Typical values are based on characterization data at V
DD
= 5.0 V, 25 C unless otherwise stated.
Max Unit
1 D Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 24 MHz
2 D Internal low-power oscillator period t
LPO
800 — 1500 s
3D
External reset pulse width
2
(t
cyc
= 1/f
Self_reset
)
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
t
extrst
100 — — ns
4 D Reset low drive t
rstdrv
66  t
cyc
——ns
5 D Active background debug mode latch setup time t
MSSU
500 — — ns
6 D Active background debug mode latch hold time t
MSH
100 — — ns
7D
IRQ pulse width
Asynchronous path
2
Synchronous path
3
3
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
t
ILIH,
t
IHIL
100
1.5  t
cyc
——ns
8D
KBIPx pulse width
Asynchronous path
2
Synchronous path
3
t
ILIH,
t
IHIL
100
1.5  t
cyc
——ns
9D
Port rise and fall time (load = 50 pF)
4
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
4
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40 C to 105 C.
t
Rise
, t
Fall
—
—
—
—
11
35
40
75
—ns
t
extrst
RESET PIN
t
IHIL
IRQ/KBIPx
t
ILIH
IRQ/KBIPx