Datasheet

MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 9
Inter-integrated circuit (IIC)
Compatible with IIC bus standard
Multi-master operation
Software programmable for one of 64 different serial clock frequencies
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Bus busy detection
10-bit address extension
Controller area network (CAN)
Implementation of the CAN protocol — Version 2.0A/B
Standard and extended data frames
Zero to eight bytes data length
Programmable bit rate up to 1 Mbps
Support for remote frames
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization using a “local priority” concept
Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, four
16-bit filters, or eight 8-bit filters
Programmable wakeup functionality with integrated low-pass filter
Programmable loopback mode supports self-test operation
Programmable listen-only mode for monitoring of CAN bus
Programmable bus-off recovery functionality
Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
Internal timer for time-stamping of received and transmitted messages
Serial communications interfaces (SCI)
Full-duplex, standard non-return-to-zero (NRZ) format
Double-buffered transmitter and receiver with separate enables
Programmable baud rates (13-bit modulo divider)
Interrupt-driven or polled operation
Hardware parity generation and checking
Programmable 8-bit or 9-bit character length
Receiver wakeup by idle-line or address-mark
Optional 13-bit break character generation / 11-bit break character detection
Selectable transmitter output polarity
Serial peripheral interfaces (SPI)
Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate