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MCF5206e

ColdFire

Integrated Microprocessor

User’s Manual

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Freescale Semiconductor, Inc.

For More Information On This Product,

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MCF5206EUM/D, rev.1

Summary of content (499 pages)

PAGE 1
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCF5206EUM/D, rev.1 MCF5206e ® ColdFire Integrated Microprocessor User’s Manual Motorola reserves the right to make changes without further notice to any products herein.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. ColdFire is a Registered Trademark of Motorola, Inc. All other trademarks reside with their respective owners. For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. DOCUMENTATION FEEDBACK FAX 512-891-8593—Documentation Comments Only (no technical questions please) http: / / www.mot.com/hpesd/docs_survey.html—Documentation Feedback Only Freescale Semiconductor, Inc... The Technical Communications Department welcomes your suggestions for improving our documentation and encourages you to complete the documentation feedback form at the World Wide Web address listed above.
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Freescale Semiconductor, Inc. Applications and Technical Information For questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. — Sales Offices — Field Applications Engineering Available Through All Sales Offices UNITED STATES Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. PREFACE The MCF5206e ColdFire® Integrated Microprocessor User’s Manual describes the programming, capabilities, and operation of the MCF5206e device. Refer to the ColdFire Family Programmer’s Reference Manual Rev 1.0 (MCF5200PRMREV1/D) for information on the ColdFire Family of microprocessors. CONTENTS Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. vi MCF5206e User’s Manual For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Introduction 1 Signal Description 2 ColdFire Core 3 Instruction Cache 4 SRAM 5 Bus Operation 6 DMA Controller Module 7 System Integration Module (SIM) 8 Chip Select Module 9 Parallel Port (General-Purpose I/O) 10 DRAM Controller 11 UART Modules 12 MBus Module 13 Timer Module 14 Debug Support 15 IEEE 1149.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1 Introduction 2 Signal Description 3 ColdFire Core 4 Instruction Cache 5 SRAM 6 Bus Operation 7 DMA Controller Module 8 System Integration Module (SIM) 9 Chip Select Module 10 Parallel Port (General-Purpose I/O) 11 DRAM Controller 12 UART Modules 13 M-Bus Module 14 Timer Module 15 Debug Support 16 IEEE 1149.
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Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Section 1 Introduction 1.1 1.2 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.9 1.3.10 1.3.11 1.3.11.1 1.3.11.2 1.3.12 1.3.13 1.3.14 1.3.15 1.3.16 1.3.17 Background ..........................................................................................1-1 MCF5206e Features .................................................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.6 2.6.1 2.6.2 2.6.3 2.7 2.7.1 2.7.2 2.7.3 2.8 2.8.1 2.8.2 2.8.3 2.9 2.9.1 2.9.2 2.9.3 2.9.4 2.10 2.10.1 2.10.2 2.11 2.11.1 2.12 2.12.1 2.12.2 2.13 2.13.1 viii Title Page Number Chip Selects .........................................................................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 2.13.2 2.14 2.14.1 2.14.2 2.14.3 2.14.4 2.14.5 2.14.6 2.15 2.15.1 2.15.2 2.15.3 2.15.4 2.15.5 2.16 2.16.1 2.16.2 2.17 Title Page Number Parallel Port (General-Purpose I/O) (PP[3:0]/DDATA[3:0]) ......2-16 Debug Support Signals ......................................................................2-16 Processor Status (PP[7:4]/PST[3:0]) ........................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.5.10 3.5.11 3.6 3.6.1 3.6.2 Title Page Number Trace Exception ......................................................................... 3-9 Debug Interrupt ........................................................................ 3-10 RTE and Format Error Exceptions ........................................... 3-10 TRAP Instruction Exceptions ......................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number Freescale Semiconductor, Inc... Section 6 Bus Operation 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.3 6.3.1 6.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.5.12 6.6 6.7 6.7.1 6.8 6.9 6.9.1 6.9.2 6.10 6.10.1 6.10.2 6.10.3 6.10.4 MOTOROLA Features ...............................................................................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 6.11 6.11.1 6.11.2 6.11.3 Title Page Number Reset Operation ................................................................................. 6-81 Master Reset............................................................................. 6-81 Normal reset ............................................................................. 6-83 Software Watchdog Timer Reset Operation ............................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 8.1.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3 8.3.1 8.3.2 8.3.2.1 8.3.2.2 8.3.2.3 8.3.2.4 8.3.2.5 8.3.2.6 8.3.2.7 8.3.2.8 8.3.2.9 8.3.2.10 8.4 8.4.1 Title Page Number Features .....................................................................................8-1 SIM Operation ......................................................................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 9.3.3.1 9.3.3.2 9.3.3.3 9.3.3.4 9.3.3.5 9.3.3.6 9.3.4 9.3.4.1 9.3.4.2 9.3.4.3 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 9.4.2.3 9.4.2.4 Title Page Number Nonburst Transfer with no Address Setup or Hold ......... 9-9 Nonburst Transfer With Address Setup ........................ 9-10 Nonburst Transfer With Address Setup and Hold ........ 9-11 Burst Transfer and Chip Selects ................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 11.3.1 11.3.1.1 11.3.1.2 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.2.4 11.3.2.5 11.3.2.6 11.3.3 11.3.3.1 11.3.3.2 11.3.4 11.3.4.1 11.3.4.2 11.3.4.3 11.3.4.4 11.3.4.5 11.3.5 11.3.6 11.3.7 11.3.8 11.3.8.1 11.3.8.2 11.3.8.3 11.3.8.4 11.4 11.4.1 11.4.2 11.4.2.1 11.4.2.2 11.4.2.3 11.4.2.4 11.4.2.5 11.5 Title Page Number Reset Operation ...................................................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 12.1.2 12.1.3 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.3.1 12.3.2 12.3.2.1 12.3.2.2 12.3.2.3 12.3.3 12.3.3.1 12.3.3.2 12.3.3.3 12.3.4 12.3.5 12.3.5.1 12.3.5.2 12.3.5.3 12.4 12.4.1 12.4.1.1 12.4.1.2 12.4.1.3 12.4.1.4 12.4.1.5 12.4.1.6 12.4.1.7 12.4.1.8 12.4.1.9 12.4.1.10 12.4.1.11 12.4.1.12 12.4.1.13 12.4.1.14 12.4.2 12.4.2.1 12.4.2.2 12.4.2.3 xvi Title Page Number Baud-Rate Generator/Timer ...
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 12.5 Title Page Number UART Module Initialization Sequence ..............................................12-34 Freescale Semiconductor, Inc... Section 13 M-Bus Module 13.1 13.2 13.3 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 13.4.8 13.4.9 13.5 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 13.6.6 13.6.7 Overview ...........................................................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Freescale Semiconductor, Inc... 14.3.4 14.4 14.4.1 14.4.1.1 14.4.1.2 14.4.1.3 14.4.1.4 14.4.1.5 Title Page Number Configuring the Timer for Output Mode .................................... 14-3 Programming Model ........................................................................... 14-3 Understanding the General-Purpose Timer Registers ............. 14-3 Timer Mode Register (TMR) .........................................
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 16.3.1 16.3.1.1 16.3.1.2 16.3.1.3 16.3.1.4 16.3.1.5 16.3.1.6 16.3.2 16.3.3 16.3.4 16.4 16.5 16.6 16.7 16.8 Title Page Number JTAG Instruction Shift Register ...............................................16-3 EXTEST Instruction .....................................................16-3 IDCODE .......................................................................16-4 SAMPLE/PRELOAD Instruction .
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Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Freescale Semiconductor, Inc... 17.3.14 17.3.15 17.3.16 17.3.17 17.3.18 17.3.19 Title Page Number General-Purpose I/O Port AC Timing Specifications ............. 17-20 General-Purpose I/O Port Timing Diagram ............................ 17-20 DMA Controller AC Timing Specifications .............................. 17-21 DMA Controller Timing Diagram ............................................ 17-21 IEEE 1149.
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number Title Page Number 1-1. 1-2. MCF5206e Block Diagram ............................................................................... 1-4 Programming Model........................................................................................ 1-8 3-1. 3-2. 3-3. 3-4. 3-5. ColdFire Processor Core Pipelines .................................................................. User Programming Model ...........
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number 6-25. 6-26. 6-27. 6-28. 6-29. 6-30. 6-31. 6-32. 6-33. 6-34. 6-35. 6-36. 6-37. 6-38. 6-39. 6-40. 6-41. Title Page Number 6-42. 6-43. 6-44. 6-45. 6-46. 6-47. 6-48. 6-49. 6-50. 6-51. Burst-Inhibited Word Read from 8 bit Port Using Async. Termination ........... 6-43 Burst-Inhibited Word-, Longword-, and Line-Write Transfer Flowchart ..........
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 9-20. Longword Burst Read Transfer from a 16 bit Port ..........................................9-16 Word Burst Read Transfer from an 8 bit Port..................................................9-18 Alternate Master Longword Read Transfer from a 32 bit Port ........................
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number Freescale Semiconductor, Inc... 11-20. Fast Page Mode Page Hit and Page Miss DRAM Transfer Timing ............. 11-56 11-21. Fast Page Mode or Burst Page Mode EDO DRAM Transfer Timing ........... 11-57 11-22. CAS Before RAS Refresh Cycle Timing ...................................................... 11-58 12-1. 12-2. 12-3. 12-4. 12-5. 12-6. 12-7. 12-8. UART Block Diagram......................................
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number 17-4. 17-5. 17-6. 17-7. 17-8. 17-9. 17-10. 17-11. 17-12. 17-13. 17-14. 17-15. 17-16. Title Page Number Reset Configuration Timing.......................................................................... 17-10 Read and Write Timing ................................................................................17-11 Bus Arbitration Timing........................................................
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Title Page Number Freescale Semiconductor, Inc... Figure Number xxvi MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. LIST OF TABLES Freescale Semiconductor, Inc... Table Number Title Page Number 1-1. 1-2. 1-3. 1-4. Specific Effective Addressing Modes .............................................................. 1-7 MOVE Specific Effective Addressing Modes ................................................. 1-7 ColdFire MCF5206e Data Formats ................................................................. 1-9 Instruction Set Summary.......................................................
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Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 5-1. 5-2. Memory Map of SIM Registers ....................................................................... 5-2 Examples of Typical RAMBAR Settings ......................................................... 5-4 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11. 6-12. 6-13. 6-14. SIZx Encoding..................................................................................
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Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. Data Bus Byte Write-Enable Signals.............................................................. 9-2 Maximum Memory Bank Sizes........................................................................ 9-4 Chip-Select, DRAM and Default Memory Address Decoding Priority ............. 9-6 Memory Map of Chip-Select Registers ........................
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Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 14-1. Programming Model for Timers .................................................................... 14-3 15-1. 15-2. 15-3. 15-4. 15-5. 15-6. 15-7. 15-8. 15-9. 15-10. 15-11. 15-12. 15-13. 15-14. Processor PST Definition.............................................................................. 15-2 CPU-Generated Message Encoding..............................................
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Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Figure Number Title Page Number Development Tools Providers ........................................................................18-3 A-1. MCF5206e User Programming Model ............................................................. A-i Freescale Semiconductor, Inc... 18-3. MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Title Page Number Freescale Semiconductor, Inc... Figure Number xxxii MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 1 Freescale Semiconductor, Inc... 2 SECTION 1 INTRODUCTION 3 1.1 BACKGROUND 4 The MCF5206e integrated microprocessor combines a Version 2 (V2) ColdFire® processor core with several peripheral functions such as a DRAM controller, timers, general-purpose I/O and serial interfaces, debug module, and system integration. Designed for embedded control applications, the V2 ColdFire core delivers enhanced performance while maintaining low system costs.
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Introduction 2 Freescale Semiconductor, Inc. separate input and output signals. For system protection, the processor includes a programmable 16-bit software watchdog timer and several bus monitors. In addition, common system functions such as chip selects, interrupt control, bus arbitration, and IEEE 1149.1 Test (JTAG) support are included. 3 A sophisticated debug interface supports both background-debug mode and real-time trace.
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Freescale Semiconductor, Inc.
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Introduction Freescale Semiconductor, Inc. — 8-bit general-purpose I/O interface 2 3 • System Debug Support — Real-time trace — Background debug interface • Fully Static 3.3-Volt Operation • Fully 5V tolerant pads on all I/O and address/data buses 4 • 160 Pin PQFP Package, pin compatible with MCF5206. • Available at 45 MHz and 54 MHz. • 3.3V with 5V-tolerant I/O. Freescale Semiconductor, Inc... • Extended temperature (-40/+85 Deg C) available. 6 7 1.
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Freescale Semiconductor, Inc. Introduction provide an overview of the integrated processor. CLOCK JTAG DRAM CONTROLLER CLOCK JTAG INTERFACE 4 KBYTE ICACHE SYSTEM BUS CONTROLLER INPUT CHIP SELECTS DRAM CONTROL CHIP SELECTS INTERRUPT CONTROLLER INTERRUPT EXTERNAL BUS INTERFACE EXTERNAL PARALLEL PORT PARALLEL SUPPORT BUS Freescale Semiconductor, Inc...
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Introduction 2 3 Freescale Semiconductor, Inc... 4 6 7 8 9 1 11 12 13 14 15 Freescale Semiconductor, Inc. 1.3.1.1 PROCESSOR STATES. The processor is always in one of four states: normal processing, exception processing, stopped, or halted. It is in the normal processing state when executing instructions, fetching instructions and operands, and storing instruction results. Exception processing is the transition from program processing to system, interrupt, and exception handling.
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Freescale Semiconductor, Inc. Introduction Table 1-1. EFFECTIVE ADDRESSING MODES AND CATEGORIES Freescale Semiconductor, Inc... ADDRESSING MODES SYNTAX CATEGORY MODE FIELD REG. FIELD DATA MEMORY CONTROL ALTERABLE Register Direct Data Address Register Indirect Address Address with Postincrement Address with Predecrement Address with Displacement Dn An 000 001 reg. no. reg. no. X — — — — — X X (An) (An)+ –(An) (d16, An) 010 011 100 101 reg. no. reg. no. reg. no. reg. no.
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Introduction 2 3 Freescale Semiconductor, Inc... 4 6 7 8 Freescale Semiconductor, Inc. The processor employs the user mode and the user programming model when it is in normal processing. During exception processing, the processor changes from user to supervisor mode. Exception processing saves the current SR value on the stack and then sets the S bit, forcing the processor into the supervisor mode.
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Freescale Semiconductor, Inc. 31 Introduction 0 D0 D1 D2 D3 DATA D4 REGISTERS D5 D6 Freescale Semiconductor, Inc... D7 31 0 A0 A1 A2 A3 ADDRESS A4 REGISTERS A5 A6 A7 STACK POINTER PC PROGRAM COUNTER CCR CONDITION CODE REGISTER USER PROGRAMMING MODEL 15 31 19 0 (CCR) MUST BE ZEROS SR STATUS REGISTER VBR VECTOR BASE REGISTER CACR CACHE CONTROL REGISTER ACR0 ACCESS CONTROL REGISTER 0 ACR1 ACCESS CONTROL REGISTER 1 Figure 1-2.
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Introduction 2 3 Freescale Semiconductor, Inc... 4 The supervisor programming model includes the upper byte of the SR, which contains operation control information. The Vector Base Register (VBR) contains the upper 12 bits of the base address of the exception vector table, which is used in exception processing. The lower 20 bits of the VBR are forced to zero, allowing the vector table to reside on any 1 Mbyte memory boundary. The Cache Control Register (CACR) controls enabling of the on-chip cache.
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Freescale Semiconductor, Inc. Introduction Table 1-3.
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Introduction Freescale Semiconductor, Inc. SUBFIELDS AND QUALIFIERS 2 3 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Introduction Table 1-4.
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Introduction Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
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Introduction Freescale Semiconductor, Inc. 1.3.6 DRAM Controller 2 3 4 The MCF5206e DRAM controller provides a glueless interface for as many as two banks of DRAM, each of which can be from 128 Kbytes to 256 Mbytes in size. The controller supports an 8 bit, 16 bit, or 32 bit data bus. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards.
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Freescale Semiconductor, Inc. Introduction need occasional bursts of rapid communication over short distances among several devices. Bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected. 1.3.11 System Interface Freescale Semiconductor, Inc...
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Introduction Freescale Semiconductor, Inc. 1.3.14 System Protection 2 3 4 The MCF5206e processor contains a 16-bit software watchdog timer with an 8-bit prescaler. The programmable software watchdog timer provides either a level 7 interrupt or a hardware reset on timeout. The MCF5206e processor also contains a reset status register that indicates the cause of the last reset. 1.3.
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Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTION 2.
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Signal Description Freescale Semiconductor, Inc. NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. Table 2-1. MCF5206e Signal Index Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Signal Description Table 2-1. MCF5206e Signal Index (Continued) Freescale Semiconductor, Inc...
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Signal Description Freescale Semiconductor, Inc. 2.2.1 Address Bus (A[27:24]/ CS[7:4]/ WE[0:3]) These multiplexed pins can serve as the most significant nibble of the address pins, chipselects, or as write enables. Programming the Pin Assignment Register (PAR) in the SIM determines the function of each of these four multiplexed pins. During reset, these pins are configured to be write enables. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Signal Description 2.3.1 Chip Selects (A[27:24]/ CS[7:4]/ WE[0:3]) These multiplexed pins can serve as the most significant nibble of the address pins, chipselects, or as write enables. Programming the Pin Assignment Register (PAR) in the SIM determines the function of each of these four multiplexed pins. During reset, these pins are configured to be write enables. The active-low chip select output signals provide control for peripherals and memory.
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Freescale Semiconductor, Inc. Signal Description Table 2-3. Byte Write Enable Signals WE[0] TRANSFER SIZE PORT SIZE BURST SIZ[1] SIZ[0] 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Signal Description Table 2-3. Byte Write Enable Signals (Continued) WE[0] TRANSFER SIZE PORT SIZE BURST SIZ[1] SIZ[0] 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 8 bit Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Signal Description Freescale Semiconductor, Inc... Table 2-4.
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Freescale Semiconductor, Inc. Signal Description 2.5.2 Size (SIZ[1:0]) These three-state bidirectional signals indicate the transfer data size for the bus cycle. When an alternate bus master is controlling the bus, the MCF5206e monitors these signals to determine the data size for asserting the appropriate memory control signals. Table 2-7 shows the definitions of the SIZ[1:0] encoding. Freescale Semiconductor, Inc... Table 2-7.
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Signal Description Freescale Semiconductor, Inc. Table 2-9.
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Freescale Semiconductor, Inc. Signal Description NOTE Freescale Semiconductor, Inc... The internal synchronized version of asynchronous transfer acknowledge (ATA) will be referred to as “internal asynchronous transfer acknowledge (ATA).” Because of the time required to internally synchronize ATA during a read cycle, data is latched on the falling edge of CLK when the internal ATA is asserted. Consequently, data must remain valid for at least one and a half clock cycles after the assertion of ATA.
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Signal Description Freescale Semiconductor, Inc. 2.6.3 Bus Driven (BD) Freescale Semiconductor, Inc... The MCF5206e asserts this active-low output signal to indicate it has assumed explicit mastership of the external bus. The MCF5206e will assert BD if BG is asserted and either the MCF5206e has a pending bus transfer or the bus lock bit in the SIMR is set to 1.
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Freescale Semiconductor, Inc. Signal Description the negation of RSTI. RSTO is also asserted for at least 31 clocks on a software watchdog timeout that is programmed to generate a reset. 2.8 DRAM CONTROLLER SIGNALS The following DRAM signals provide a glueless interface to external DRAM. Freescale Semiconductor, Inc... 2.8.1 Row Address Strobes (RAS[1:0]) These active-low output signals provide control for the row address strobe (RAS) input pins on industry-standard DRAMs.
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Signal Description Freescale Semiconductor, Inc. Table 2-10. CAS Assertion (Continued) CAS[0] OPERAND SIZE PORT SIZE SIZ[1] SIZ[0] 8 bit 1 0 16 bit 1 0 32 bit 1 0 8 bit 0 0 16 bit 0 0 32 bit 0 0 8 bit 1 1 16 bit 1 1 32 bit 1 1 A[1] A[0] 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Signal Description 2.9.2 Transmit Data (TxD[1], TxD[2]) The UART modules transmit serial data on these outputs. TxD[1] corresponds to UART 1 and TxD[2] corresponds to UART 2. Data is transmitted on the falling edge of the serial clock source, with the least significant bit transmitted (LSB) first. When no data is being transmitted or the transmitter is disabled, these two signals are held high. TxD[1] and TxD[2] are also held high in local loopback mode. 2.9.
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Signal Description Freescale Semiconductor, Inc. mode of operation. Programming the Pin Assignment Register (PAR) in the SIM determines the function of these pins. The DMA channels can be programmed for singleand dual-address mode, with the ability to program bursting and cycle steal. Data transfers are 32 bits in length with packing and unpacking supported, along with an autoalignment option for efficient block transfers. 2.12 M-BUS MODULE SIGNALS Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Signal Description These outputs indicate the MCF5206e processor status. During debug mode, the timing is synchronous with the processor clock (CLK) and the status is not related to the current bus transfer. Table 2-11 shows the encodings of PST[3:0]. . Table 2-11. Processor Status Encodings Freescale Semiconductor, Inc...
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Signal Description Freescale Semiconductor, Inc. 2.14.4 Break Point (TMS/BKPT) The MTMOD signal determines the function of this dual-purpose pin. If MTMOD = 0, then the TMS function is selected. If MTMOD =1, the BKPT function is selected. MTMOD should not change while RSTI = 1. The assertion of the active-low BKPT input signal causes a hardware breakpoint to occur in the processor when in the Debug mode. See Section 15: Debug Support section for additional information on this signal.
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Freescale Semiconductor, Inc. Signal Description not driven low, its value will default to a logic level of 1. However, if JTAG is not used, TRST can either be tied to ground or, if TCK is clocked, it can be tied to VDD. The former connection places the JTAG controller in the test logic reset state immediately, while the latter connection causes the JTAG controller (if TMS is a logic 1) to eventually end up in the test logic reset state after five clocks of TCK. 2.15.
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Signal Description Freescale Semiconductor, Inc. 2.16 TEST SIGNALS 2.16.1 Motorola Test Mode (MTMOD) This input signal chooses between the debug and JTAG signals that are multiplexed together. When MTMOD=1, the MCF5206e is in Debug mode and when MTMOD=0, the MCF5206e is in JTAG mode. Freescale Semiconductor, Inc... 2.16.2 High Impedance (HIZ) The assertion of the HIZ input signal forces all output drivers to a high-impedance state (three-state). The timing on HIZ is independent of the clock.
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Freescale Semiconductor, Inc. Signal Description Freescale Semiconductor, Inc... Table 2-12.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Signal Description 2-22 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 1 2 SECTION 3 COLDFIRE CORE 3 Freescale Semiconductor, Inc... This section describes the organization of the Version 2 (V2) ColdFire® 5200 processor core and an overview of the program-visible registers. For detailed information on instructions, see the ColdFire Family Programmer’s Reference Manual. 4 5 3.1 PROCESSOR PIPELINES Figure 3-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
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ColdFire Core 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 12 13 14 15 Freescale Semiconductor, Inc. The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The Instruction Fetch Pipeline (IFP) is responsible for instruction address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP).
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Freescale Semiconductor, Inc. ColdFire Core 1 31 15 7 0 Freescale Semiconductor, Inc... D0 D1 D2 D3 D4 D5 D6 D7 15 7 3 A0 A1 A2 A3 A4 A5 A6 ADDRESS REGISTERS A7 STACK POINTER PC PROGRAM COUNTER CCR CONDITION CODE REGISTER 0 2 DATA REGISTERS 5 6 Figure 3-2. User Programming Model 7 3.2.1.5 CONDITION CODE REGISTER . The CCR is the least significant byte of the processor status register (SR). Bits 4–0 represent indicator flags based on results generated by processor operations.
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ColdFire Core 1 2 Freescale Semiconductor, Inc. 3.2.2 MAC Unit User Programming Model The MAC portion of the user programming model available on the 5206e microprocessor core is shown below. It consists of the following registers: • 32-bit accumulator (ACC) 3 • 16-bit mask register (MASK) • 8-bit MAC status register (MACSR) 4 31 15 7 ACC MASK Freescale Semiconductor, Inc... 5 6 7 8 9 10 MACSR Figure 3-3. MAC Unit User Programming Model 3.2.
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Freescale Semiconductor, Inc. ColdFire Core bits indicate the following states for the processor: trace mode (T-bit), supervisor or user mode (S bit), and master or interrupt state (M). 15 T 14 0 SYSTEM BYTE 13 12 11 10 S M 0 9 I[2:0] 8 7 0 CONDITION CODE REGISTER (CCR) 6 5 4 3 2 1 0 0 X N Z V 1 2 0 C Status Register 3 Freescale Semiconductor, Inc... T– trace enable When set, the processor will perform a trace exception after every instruction.
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ColdFire Core 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 Freescale Semiconductor, Inc. First, the processor makes an internal copy of the SR and then enters supervisor mode by asserting the S bit and disabling trace mode by negating the T bit. The occurrence of an interrupt exception also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request. Second, the processor determines the exception vector number.
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Freescale Semiconductor, Inc. ColdFire Core 1 Table 3-1.
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ColdFire Core 1 Table 3-2. Format Field Encodings 2 3 4 Freescale Semiconductor, Inc... 7 8 9 13 14 15 A7 @ 1ST INSTRUCTION OF HANDLER FORMAT FIELD 00 01 10 11 Original A7 - 8 Original A7 - 9 Original A7 - 10 Original A7 - 11 4 5 6 7 Table 3-3. Fault Status Encodings 6 12 ORIGINAL A7 @ TIME OF EXCEPTION, BITS 1:0 • There is a 4-bit fault status field, FS[3:0], at the top of the system stack.
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Freescale Semiconductor, Inc. ColdFire Core Freescale Semiconductor, Inc... register updates attributable to the auto-addressing modes, (e.g., (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, any registers already updated before the fault occurs contains the operands from memory.
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ColdFire Core 1 2 3 Freescale Semiconductor, Inc. Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider the execution of a TRAP instruction while in trace mode. The processor will initiate the TRAP exception and then pass control to the corresponding handler.
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Freescale Semiconductor, Inc. ColdFire Core 1 3.5.10 Fault-on-Fault Halt If a V2 processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition. A reset is required to force the processor to exit this halted state. 2 3.5.11 Reset Exception 3 Freescale Semiconductor, Inc... Asserting the reset input signal to the processor causes a reset exception.
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ColdFire Core 1 2 3 4 Freescale Semiconductor, Inc... 5 6 Freescale Semiconductor, Inc. 1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words. 2. The OEP does not experience any sequence-related pipeline stalls.
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Freescale Semiconductor, Inc. ColdFire Core 1 Table 3-5. Move Byte and Word Execution Times DESTINATION SOURCE Freescale Semiconductor, Inc... Dn An (An) (An)+ -(An) (d16,An) RX (AX) (AX)+ -(AX) (D16,AX) (D8,AX,XI) (XXX).
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Freescale Semiconductor, Inc. ColdFire Core 1 3.7 STANDARD ONE OPERAND INSTRUCTION EXECUTION TIMES Table 3-7. One Operand Instruction Execution Times 2 EFFECTIVE ADDRESS 3 4 Freescale Semiconductor, Inc... 5 6 7 OPCODE CLR.B CLR.W CLR.L EXT.W EXT.L EXTB.L NEG.L NEGX.L NOT.L Scc SWAP TST.B TST.W TST.L Dx Dx Dx Dx Dx Dx Dx Dx RN (AN) (AN)+ -(AN) (D16,AN) (D8,AN,XN*SF) XXX.
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Freescale Semiconductor, Inc. ColdFire Core 1 3.8 STANDARD TWO OPERAND INSTRUCTION EXECUTION TIMES Table 3-8. Two Operand Instruction Execution Times 2 EFFECTIVE ADDRESS Freescale Semiconductor, Inc... OPCODE RN (AN) (AN)+ -(AN) (D16,AN) (D16,PC) (D8,AN,XN*SF) (D8,PC,XN*SF) XXX.WL #XXX ADD.L ADD.L ADDI.L ADDQ.L ADDX.L AND.L AND.L ANDI.L ASL.L ASR.L BCHG BCHG BCLR BCLR BSET BSET BTST BTST CMP.L CMPI.L DIVS.W DIVU.W DIVS.L DIVU.L EOR.L EORI.L LEA LSL.L LSR.L MAC.W MAC.L MSAC.W MSAC.L MAC.
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ColdFire Core 1 2 3 4 Freescale Semiconductor, Inc. Table 3-8. Two Operand Instruction Execution Times EFFECTIVE ADDRESS OPCODE ORI.L SUB.L SUB.L SUBI.L SUBQ.L SUBX.L #imm,Dx ,Rx Dy, #imm,Dx #imm, Dy,Dx RN (AN) (AN)+ -(AN) (D16,AN) (D16,PC) (D8,AN,XN*SF) (D8,PC,XN*SF) XXX.
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Freescale Semiconductor, Inc. ColdFire Core 1 3.9 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Table 3-9. Miscellaneous Instruction Execution Times 2 Freescale Semiconductor, Inc... EFFECTIVE ADDRESS OPCODE RN (AN) (AN)+ -(AN) (D16,AN) (D8,AN,XN*SF) XXX.WL #XXX LINK.W MOVE.W MOVE.W MOVE.W Ay,#imm CCR,Dx ,CCR SR,Dx 2(0/1) 1(0/0) 1(0/0) 1(0/0) — — — — — — — — — — — — — — — — — — — — — — — — — — 1(0/0) — MOVE.W ,SR 7(0/0) — — — — — — MOVEC Ry,Rc MOVEM.
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Freescale Semiconductor, Inc. ColdFire Core 1 3.10 BRANCH INSTRUCTION EXECUTION TIMES Table 3-10. General Branch Instruction Execution Times 2 EFFECTIVE ADDRESS OPCODE 3 4 BSR JMP JSR RTE RTS 5 RN (AN) (AN)+ -(AN) (D16,AN) (D16,PC) (D8,AN,XI*SF) (D8,PC,XI*SF) XXX.WL #XXX — — — — — — 3(0/0) 3(0/1) — — — — — 10(2/0) 5(1/0) — — — — — 3(0/1) 3(0/0) 3(0/1) — — — 4(0/0) 4(0/1) — — — 3(0/0) 3(0/1) — — — — — — — Freescale Semiconductor, Inc... Table 3-11.
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Freescale Semiconductor, Inc. SECTION 4 INSTRUCTION CACHE 4.1 FEATURES OF INSTRUCTION CACHE • 4 KByte Direct-Mapped Cache Freescale Semiconductor, Inc... • Single-Cycle Access on Cache Hits • Physically Located on ColdFire® Core's High-Speed Local Bus • Nonblocking Design to Maximize Performance • 16 Byte Line-Fill Buffer • Configurable Cache Miss-Fetch Algorithm 4.
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Freescale Semiconductor, Inc. Instruction Cache The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer. EXTERNAL DATA[31:0] 31 LOCAL ADDRESS BUS 11 31 4 3 21 0 4 LINE BUFFER DATA STORAGE BUFFER ADDRESS Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Instruction Cache 4.3.1 Interaction With Other Modules Because both the instruction cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous instruction fetch processing. If the referenced address is mapped into the SRAM module, that module will service the request in a single cycle.
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Instruction Cache Freescale Semiconductor, Inc. These invalidation operations can be initiated from the ColdFire core or the debug module. 4.3.4 RESET A hardware reset clears the CACR disabling the instruction cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[24] before the cache can be enabled. Freescale Semiconductor, Inc... 4.3.
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Freescale Semiconductor, Inc. Instruction Cache Freescale Semiconductor, Inc... contents of the fill buffer versus its corresponding cache location. At the time of the miss, the hardware indicator is set, marking the fill buffer as “most recently used.” If a subsequent access occurs to the cache location defined by bits [8:4] of the fill buffer address, the data in the cache memory array is now most recently used, so the hardware indicator is cleared.
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Freescale Semiconductor, Inc. Instruction Cache • Addresses not assigned to the registers and undefined register bits are reserved for future expansion. Write accesses to these reserved address spaces and reserved register bits have no effect; read accesses will return zeros. • The reset value column indicates the initial value of the register at reset. Certain registers may be uninitialized upon reset, i.e., they may contain random values after reset. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Instruction Cache CENB - Cache Enable Generally, longword references are used for sequential fetches. If the processor branches to an odd word address, a word-sized fetch is generated. The memory array of the instruction cache is enabled only if CENB is asserted. 0 = Cache disabled 1 = Cache enabled Freescale Semiconductor, Inc...
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Instruction Cache Freescale Semiconductor, Inc. DCM - Default Cache Mode This bit defines the default cache mode: 0 is cacheable, 1 is noncacheable. For more information on the selection of the effective memory attributes, see Section 4.3.2 Memory Reference Attributes. Freescale Semiconductor, Inc... 0 = Deafault cacheable 1 = Default noncacheable DBWE - Default Buffered Write Enable This bit defines the default value for enabling buffered writes.
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Freescale Semiconductor, Inc. Instruction Cache The ACRs are 32-bit write-only supervisor control registers. They are accessed in the CPU address space via the MOVEC instruction with an Rc encoding of $004 and $005. The ACRs can be read when in background debug mode (BDM). At system reset, the registers are cleared. Freescale Semiconductor, Inc...
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Instruction Cache Freescale Semiconductor, Inc. CM - Cache Mode This bit defines the cache mode: 0 is cacheable, 1 is noncacheable. Freescale Semiconductor, Inc... 0 = Caching enabled 1 = Caching disabled BWE- Buffered Write Enable This bit defines the value for enabling buffered writes. If BWE = 0, the termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is completed.
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Freescale Semiconductor, Inc. SECTION 5 SRAM 5.1 SRAM FEATURES • 8 KByte SRAM, organized as 2K x 32 Bits Freescale Semiconductor, Inc... • Single-Cycle Access • Physically Located on ColdFire® core's High-Speed Local Bus • Byte, Word, Longword Address Capabilities • Memory Mapping Defined by the Customer 5.2 SRAM OPERATION The SRAM module provides a general-purpose memory block that the ColdFire core can access in a single cycle.
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Freescale Semiconductor, Inc. SRAM • The access column indicates if the corresponding register allows both read/write functionality (R/W), read-only functionality (R), or write-only functionality (W). If a read access to a write-only register is attempted, zeros will be returned. If a write access to a read-only register is attempted the access will be ignored and no write will occur. Freescale Semiconductor, Inc... Table 5-1.
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Freescale Semiconductor, Inc. SRAM C/I, SC, SD, UC, UD - Address Space Masks This field allows specific address spaces to be enabled or disabled, placing the internal modules in a specific address space. If an address space is disabled, an access to the register location in that address space becomes an external bus access, and the module resource is not accessed. The address space mask bits are: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. SRAM address space. 2. Read the source data and write it to the SRAM. There are various instructions to support this function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance. 3.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 6 BUS OPERATION The MCF5206e bus interface supports synchronous data transfers that can be terminated synchronously or asynchronously and also can be burst or burst-inhibited between the MCF5206e and other devices in the system. This section describes the function of the bus, the signals that control the bus, and the bus cycles provided for data-transfer operations.
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Bus Operation Freescale Semiconductor, Inc. NOTE The ColdFire® core outputs 32 bits of address to the internal bus controller. Of these 32 bits, only A[27:0] are output to pins on the MCF5206e. The output of A[27:24] depends on the setting of PAR[3:0] in the Pin Assignment Register (PAR) in the SIM. Refer to 6.3.2.10 Pin Assignment Register on how to program the Pin Assignment Register (PAR). Freescale Semiconductor, Inc... 6.2.
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Freescale Semiconductor, Inc. Bus Operation 6.2.6 Transfer Type (TT[1:0]) These three-state output signals indicate the type of access for the current bus cycle. Table 6-2 lists the definitions of the TTx encodings. Table 6-2. Transfer Type Encoding TT1 TT0 TRANSFER TYPE 0 0 1 1 0 1 0 1 Normal Access On-board DMA Access Debug Access CPU Space/Acknowledge Access Freescale Semiconductor, Inc... The MCF5206e does not sample TT[1:0] during external master transfers. 6.2.
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Bus Operation Freescale Semiconductor, Inc. 6.2.8 Asynchronous Transfer Acknowledge (ATA) This active-low asynchronous input signal indicates the successful completion of a requested data transfer operation. Asynchronous transfer acknowledge (ATA) is an input signal from the referenced slave device indicating completion of the transfer. ATA is synchronized internal to the MCF5206e. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Operation to a chip select or default memory, the assertion of TA is controlled by the number of wait states and the setting of the external master automatic acknowledge (EMAA) bit in the Chip Select Control Registers (CSCRs) or the Default Memory Control Register (DMCR). If the external master-requested transfer is a DRAM access, the MCF5206e drives TA as an output and is asserted at the completion of the transfer. 6.2.
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Freescale Semiconductor, Inc. Bus Operation Outputs to the MCF5206e begin to transition on the rising CLK edges, with the exception of RAS[1:0] and CAS[3:0], which begin to transition on the falling CLK edges. Specifically, RAS[1:0] is asserted and negated synchronous with the falling edge of CLK, while CAS[3:0] is asserted synchronous with the falling edge of CLK and can be negated synchronous with either the falling edge or the rising edge of CLK.
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Freescale Semiconductor, Inc. Bus Operation Address Registers (CSAR), DRAM Controller Address Registers (DCARs), the Chip Select Mask Registers (CSMR), and DRAM Controller Mask Registers (DCMR), looking for a match. The priority is listed in Table 6-4 (from highest priority to lowest priority): Table 6-4. Chip Select, DRAM and Default Memory Address Decoding Priority Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Operation 31 0 OP0 OP2 OP1 OP3 15 LONGWORD OPERAND 0 OP2 OP3 7 WORD OPERAND 0 OP3 BYTE OPERAND Freescale Semiconductor, Inc... Figure 6-2. Internal Operand Representation Figure 6-3 shows the required organization of data ports on the MCF5206e for 8-, 16-, and 32 bit devices. The four bytes shown are connected through the internal data bus and data multiplexer to the external data bus.
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Freescale Semiconductor, Inc. Bus Operation The MCF5206e can burst anytime the port size of the external slave being accessed is smaller than the operand size. If bursting is enabled, the MCF5206e performs burst transfers depending on the port size and operand alignment. For any transfer, the number of bytes transferred during a bus cycle is equal to or less than the size indicated by the SIZx outputs.
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Freescale Semiconductor, Inc. Bus Operation Table 6-7. Data Bus Requirement for Read Cycles SIZE TRANSFER SIZE ADDRESS SIZ[1] SIZ[0] BYTE 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Operation Figure 6-4 is a flowchart for read transfers to 8-, 16-, or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the transfer, and the specific number of cycles needed for each transfer. Freescale Semiconductor, Inc... MCF5206e 1. DRIVE ADDRESS ON A[27:0] SYSTEM 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-5 shows a longword supervisor code read from a 32-bit port. C1 C2 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $0 D[31:0] TA TEA ATA Figure 6-5. Longword-Read Transfer From a 32-Bit Port (No Wait States) Clock 1 (C1) The read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Bus Operation TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. Table 6-8 lists the combinations of SIZ[1:0], A[1:0] and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MCF5206e to the external data bus. For example, if a longword transfer is generated to a 16-bit port, the MCF5206e starts the cycle with A[1:0] set to $0 and read the first word.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-6 is a flowchart for write transfers to 8-, 16-, or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the transfer and the specific number of cycles needed for each transfer. MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO WRITE (R/W = 0) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-7 shows a supervisor data word-write transfer to a 16-bit port. C1 C2 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $2 D[31:0] TA TEA ATA Figure 6-7. Word-Write Transfer to a 16-Bit Port (No Wait States) Clock 1 (C1) The write cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Bus Operation Freescale Semiconductor, Inc. 6.5.2 Bursting Read Transfers: Word, Longword, and Line Freescale Semiconductor, Inc... If the burst-enable bit in the appropriate control register (Chip Select Control Register or Default Memory Control Register) is set to 1or the transfer is to DRAM, and the operand size is larger than the port size of the memory being accessed, the MCF5206e performs word, longword, and line transfers in burst mode.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCF5206e 1. DRIVE ADDRESS ON A[27:0] Bus Operation SYSTEM 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 1. 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE DECODE ADDRESS AND SELECT THE APPROPRIATE SLAVE DEVICE.* 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-9 shows a bursting user code word-read transfer from an 8-bit port. C1 C2 C3 CLK TS A[27:1] $ADDR A[0] Freescale Semiconductor, Inc... R/W TT[1:0] $0 ATM SIZ[1:0] $2 D[31:24] TA TEA ATA Figure 6-9. Bursting Word-Read From an 8-Bit Port (No Wait States) Clock 1 (C1) The read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Bus Operation Clock 3 (C3) The MCF5206e increments A0 to address the next byte of the word transfer. The selected device(s) places the second byte of the addressed data onto D[31:24] and asserts the transfer acknowledge (TA). At the end of C3, the MCF5206e samples the level of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the word read is complete and the transfer is terminated.
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Freescale Semiconductor, Inc. Bus Operation Freescale Semiconductor, Inc... MCF5206e SYSTEM 1. DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO WRITE (R/W = 0) 3. DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 3. DRIVE DATA ON APPROPRIATE BYTE LANES BASED ON SIZ[1:0], A[1:0] AND PORT SIZE 1. RECOGNIZE THE 1ST TRANSFER IS DONE 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-11 shows a user data bursting line-write transfer to a 32-bit port. C1 C3 C2 C4 C5 CLK TS A[27:4] $ADDR A[3:2] $2 $3 $0 $1 Freescale Semiconductor, Inc... A[1:0] R/W TT[1:0] $0 ATM SIZ[1:0] $3 D[31:0] TA TEA ATA Figure 6-11. Line-Write Transfer to a 32-Bit Port (No Wait States) Clock 1 (C1) The write cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Bus Operation Freescale Semiconductor, Inc. continues to output the data and inserts wait states instead of terminating the transfer. The MCF5206e continues to sample TA on successive rising edges of CLK until it is asserted. Clock 3 (C3) Freescale Semiconductor, Inc... The MCF5206e increments A[3:2] to address the next longword of the line transfer and drives D[31:0] with the second longword of data. The selected device(s) asserts the TA if it is ready to latch the data.
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Freescale Semiconductor, Inc. Bus Operation Freescale Semiconductor, Inc... The basic transfer of a burst-inhibited read is the same as a “normal” read with the addition of more transfers until the entire operand has been accessed. Burst-inhibited read transfers can be from two to sixteen transfers long. Figure 6-12 is a flowchart for burstinhibited read transfers (4 transfers long) to 8-, 16-, or 32-bit ports.
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Freescale Semiconductor, Inc. Bus Operation MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 1. REGISTER DATA 2. RECOGNIZE THE 1ST TRANSFER IS DONE 1. INCREMENT APPROPRIATE ADDRESS BITS BASED ON A[3:0] AND PORT SIZE 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-13 shows a burst-inhibited supervisor code longword-read transfer from an 8-bit port. C1 C2 C3 C4 C5 C6 C7 C8 CLK TS A[27:2] $ADDR A[1:0] $0 $1 $2 $3 Freescale Semiconductor, Inc... R/W TT[1:0] $0 ATM SIZ[1:0] $1 D[31:24] TA TEA ATA Figure 6-13. Burst-Inhibited Longword Read From an 8-Bit Port (No Wait States) Clock 1 (C1) The read cycle starts in C1.
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Bus Operation Freescale Semiconductor, Inc. sample TA and inserts wait states instead of terminating the transfer. The MCF5206e continues to sample TA on successive rising edges of CLK until it is asserted. Clock 3 (C3) The MCF5206e increments A[1:0] to address the second byte of the longword transfer. The MCF5206e continues to drive transfer type (TT[1:0]), read/write (R/W) and size (SIZ[1:0]) signals to indicate a byte read. Access transfer mode (ATM) is driven high to indicate the transfer as code.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-14. Burst-Inhibited Byte-, Word-, and Longword-Write Transfer Flowchart MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO WRITE (R/W = 0) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 3.
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Bus Operation Freescale Semiconductor, Inc. Figure 6-15 shows a burst-inhibited supervisor data longword-write transfer to a 16-bit port. C1 C2 C3 C4 CLK TS A[27:2] $ADDR A[1:0] $0 $2 Freescale Semiconductor, Inc... R/W TT[1:0] $0 ATM SIZ[1:0] $2 D[31:0] TA TEA ATA Figure 6-15. Burst-Inhibited Longword-Write Transfer to a 16-Bit Port (No Wait States) Clock 1 (C1) The write cycle starts in C1.
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Freescale Semiconductor, Inc. Bus Operation the data and inserts wait states instead of terminating the transfer. The MCF5206e continues to sample TA on successive rising edges of CLK until it is asserted. Clock 3 (C3) The MCF5206e increments A[1:0] to address the next word, asserts TS and drives ATM low to identify the transfer as code or data. Clock 4 (C4) Freescale Semiconductor, Inc... This clock is identical to C2 except that the data driven corresponds to the second word of data.
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Freescale Semiconductor, Inc. Bus Operation the portion of the data bus used for the transfer, and the specific number of cycles needed for each transfer. MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 1. REGISTER DATA 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-17 shows a user code byte read from an 8-bit port. C1 C2 C3 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $1 D[31:24] TA TEA ATA INTERNAL ATA Figure 6-17. Byte-Read Transfer from an 8-Bit Port Using Asynchronous Termination (One Wait State) Clock 1 (C1) The read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Bus Operation Clock 3 (C3) Freescale Semiconductor, Inc... At the end of C3, the MCF5206e samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:24]. If internal asynchronous transfer acknowledge is asserted, the byte transfer is complete and the transfer terminates.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-19 shows a user data byte transfer to a 32-bit port with asynchronous termination. C1 C2 C3 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $1 D[31:0] TA TEA ATA INTERNAL ATA Figure 6-19. Byte-Write Transfer to a 32-Bit Port Using Asynchronous Termination (One Wait State) Clock 1 (C1) The write cycle starts in C1.
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Bus Operation Freescale Semiconductor, Inc. Clock 3 (C3) Freescale Semiconductor, Inc... At the end of C3, the MCF5206e samples the level of internal asynchronous transfer acknowledge and if it is asserted, the transfer of the byte is complete and the transfer terminates. If internal asynchronous transfer acknowledge is negated, the MCF5206e continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer.
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Freescale Semiconductor, Inc. Bus Operation The flow chart shown is for four bursting transfers. MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 1. REGISTER DATA 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-21 shows a bursting supervisor data longword-read transfer from a 16-bit port. C1 C2 C3 C4 C5 CLK TS A[27:2] $ADDR A[1] Freescale Semiconductor, Inc... A[0] R/W TT[1:0] $0 ATM SIZ[1:0] $0 D[31:16] TA TEA ATA INTERNAL ATA Figure 6-21. Bursting Longword-Read from 16-Bit Port Using Asynchronous Termination (One Wait State) Clock 1 (C1) The read cycle starts in C1.
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Freescale Semiconductor, Inc. Bus Operation Clock 2 (C2) During C2, the MCF5206e negates TS, drives ATM high to identify the transfer as supervisor. The selected device(s) asserts ATA prior to the falling edge of the clock. Freescale Semiconductor, Inc... Clock 3 (C3) At the end of C3, the MCF5206e samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:16].
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Freescale Semiconductor, Inc. Bus Operation MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO WRITE (R/W = 0) 3. DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 3. DRIVE DATA ON APPROPRIATE BYTE LANES BASED ON SIZ[1:0], A[1:0] AND PORT SIZE 1. 1.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-23 shows a bursting user data line-write transfer to a 32-bit port using asynchronous termination. C2 C1 C3 C4 C5 C6 C7 C8 C9 CLK TS $ADDR A[27:4] $0 Freescale Semiconductor, Inc... A[3:2] $1 $2 $3 A[1:0] R/W TT[1:0] $0 ATM SIZ[1:0] $3 D[31:0] TA TEA ATA INTERNAL ATA Figure 6-23. Bursting Line-Write from 32-Bit Port Using Asynchronous Termination (One Wait State) Clock 1 (C1) The write cycle starts in C1.
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Bus Operation Freescale Semiconductor, Inc. Clock 2 (C2) During C2, the MCF5206e negates TS, drives ATM low to identify the transfer as user and places the data on the data bus (D[31:0]). The selected device(s) asserts ATA if it is ready to latch the data, which is recognized by the MCF5206e on the next falling clock edge. Freescale Semiconductor, Inc... Clock 3 (C3) If the selected device asserted asynchronous transfer acknowledge during C2, the selected device must latch the data by the end of C3.
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Freescale Semiconductor, Inc. Bus Operation Clock 9 (C9) This clock is identical to C3 except that the data value corresponds to the fourth longword of data for the line. This is the last CLK cycle of the line write transfer and the MCF5206e three-states D[31:0] at the start of the next CLK cycle. Freescale Semiconductor, Inc... 6.5.
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Bus Operation Freescale Semiconductor, Inc. MCF5206e Freescale Semiconductor, Inc... 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 1. 1. REGISTER DATA 2. RECOGNIZE THE 1ST TRANSFER IS DONE 1.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-25 shows a burst-inhibited user code word-read transfer from an 8-bit port. C1 C2 C3 C4 C5 C6 CLK TS A[27:1] $ADDR A[0] Freescale Semiconductor, Inc... R/W TT[1:0] $0 ATM SIZ[1:0] $1 D[31:24] TA TEA ATA INTERNAL ATA Figure 6-25. Burst-Inhibited Word Read from 8-Bit Port Using Asynchronous Termination Clock 1 (C1) The read cycle starts in C1.
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Bus Operation Freescale Semiconductor, Inc. Clock 3 (C3) Freescale Semiconductor, Inc... At the end of C3, the MCF5206e samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:24]. If internal asynchronous transfer acknowledge is asserted, the transfer of the first byte is complete.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1. DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO WRITE (R/W = 0) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE 5. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE 3. DRIVE DATA ON APPROPRIATE BYTE LANES BASED ON SIZ[1:0], A[1:0] AND PORT SIZE 1. RECOGNIZE THE 1ST TRANSFER IS DONE 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-27 shows a burst-inhibited supervisor data longword-write transfer to a 16-bit port. C1 C2 C3 C4 C5 C6 CLK TS A[27:2] $ADDR Freescale Semiconductor, Inc... A[1] A[0] R/W TT[1:0] $0 ATM SIZ[1:0] $2 D[31:0] TA TEA ATA INTERNAL ATA Figure 6-27. Burst-Inhibited Longword-Write Transfer to 16-Bit Port Using Asynchronous Termination (One Wait State) Clock 1 (C1) The write cycle starts in C1.
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Freescale Semiconductor, Inc. Bus Operation Clock 2 (C2) During C2, the MCF5206e negates TS, drives ATM high to identify the transfer as supervisor and drives the data on the data bus (D[31:0]). The selected device(s) asserts ATA if it is ready to latch the data. Freescale Semiconductor, Inc... Clock 3 (C3) At the end of C3, the MCF5206e samples the level of internal asynchronous transfer acknowledge and if it is asserted, terminates the first word transfer.
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Freescale Semiconductor, Inc. Bus Operation NOTE TA cannot be tied to GND if the MCF5206e is not the only bus master in the system. Damage to the part could occur if TA is tied to GND and external master accesses using 5206e generated termination. Freescale Semiconductor, Inc... 6.6 MISALIGNED OPERANDS All MCF5206e data formats can be located in memory on any byte boundary.
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Freescale Semiconductor, Inc. Bus Operation NOTE External masters that are using internal MCF5206e chip selects, DRAM, and default memory control signals must initiate aligned transfers only. 6.7 ACKNOWLEDGE CYCLES Freescale Semiconductor, Inc... When a peripheral device requires the services of the MCF5206e or is ready to send information that the ColdFire core requires, it can signal the ColdFire core to take an interrupt exception.
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Freescale Semiconductor, Inc. Bus Operation NOTE If autovector generation is used for external interrupts, no interrupt acknowledge cycle is generated on the external bus. Consequently, the user must clear the external interrupt in the interrupt service routine. 6.7.1 Interrupt Acknowledge Cycle Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Operation Figure 6-31 shows an interrupt acknowledge cycle. C1 C2 CLK TS A[27:5] $INT_LEVEL Freescale Semiconductor, Inc... A[4:2] A[1:0] R/W TT[1:0] $3 ATM SIZ[1:0] $1 D[31:24] TA TEA ATA Figure 6-31. Interrupt Acknowledge Bus Cycle Timing (No Wait States) Clock 1 (C1) The interrupt acknowledge cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Bus Operation device(s) places the interrupt vector number onto D[31:24] and asserts TA. At the end of C2, the MCF5206e samples the level of TA and if TA is asserted, latches the current value of D[31:24] which contains the interrupt vector number. If TA is asserted, the transfer of the interrupt vector is complete and the transfer terminates. If TA is negated, the MCF5206e continues to sample TA and inserts wait states instead of terminating the transfer.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-32 shows a bursting supervisor code longword-read access from a 16-bit port with a transfer error. C1 C2 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $0 D[31:0] TA TEA ATA Figure 6-32. Bursting Longword-Read Access from 16-Bit Port Terminated with TEA Timing Clock 1 (C1) The read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Bus Operation Freescale Semiconductor, Inc. NOTE If TA is asserted when transfer error-acknowledge (TEA) is asserted, the transfer is terminated with a bus error. NOTE For the MCF5206e to accept the transfer as successful with an ATA, TEA must be negated until the internal asynchronous transfer acknowledge is asserted or the transfer is completed with a bus error. Freescale Semiconductor, Inc... 6.
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Freescale Semiconductor, Inc. Bus Operation Freescale Semiconductor, Inc... two-wire mode. In this mode, the active-low bus grant (BG) input of the MCF5206e is connected to the active-high HOLDREQ output of the external bus master and the activelow bus-driven (BD) output of the MCF5206e is connected to the active-high HOLDACK input of the external bus master.
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Bus Operation Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCF5206e continues to assert BD until the completion of the bus cycle. If bus grant (BG) is negated by the end of the bus cycle and the Bus Lock bit in the SIMR is 0, the MCF5206e negates BD. As long as bus grant (BG) is asserted, BD remains asserted to indicate the bus is owned by the MCF5206e and the MCF5206e continuously drives the address bus, attributes and control signals.
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Freescale Semiconductor, Inc. C1 C2 C3 C4 C5 C6 C7 Bus Operation C8 C9 CLK A[27:0] TRANSFER ATTRIBUTES Freescale Semiconductor, Inc... TS TA D[31:0] BG BD BUS LOCK BIT IMPLICIT OWNERSHIP EXTERNAL MASTER EXPLICIT OWNERSHIP MCF5206e then an internal bus request being generated. Figure 6-34. Two-Wire Implicit and Explicit Bus Ownership In Figure 6-34, the external master has ownership of the external bus during Clock 1 (C1) and Clock 2 (C2).
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Freescale Semiconductor, Inc. Bus Operation When the bus has been removed from the MCF5206e, one of two situations can occur. In the first case, the bus lock bit in the SIM Configuration Register (SIMR) is cleared and the MCF5206e has implicit ownership of the bus. When the external bus master negates BG, the MCF5206e negates BD and three-state the address, data, TS, R/W, and SIZ signals after completing the current bus cycle. Figure 6-35 illustrates two-wire bus arbitration with the bus lock bit cleared.
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Freescale Semiconductor, Inc. Bus Operation mastership of the bus is controlled by an external master. In this fashion, the MCF5206e can be guaranteed mastership of the bus when executing time critical, bus intensive operations. Figure 6-36 illustrates bus arbitration using the bus lock bit to control the arbitration. C1 C2 C3 C4 C5 C6 C7 C8 C9 CLK A[27:0] Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Operation each state of the bus arbitration state machine. A1 A2 RESET A4 A3 B1 Freescale Semiconductor, Inc... EM OWN IMPLICIT B3 OWN D3 D2 D4 B2 B4 C3 C5 EXPLICIT OWN C1 C2 C4 Figure 6-37. MCF5206e Two-Wire Bus Arbitration Protocol State Diagram Table 6-10.
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Freescale Semiconductor, Inc. Bus Operation NOTES 1)“N” means negated; “A” means asserted; “EM” means external master. 2)End of Cycle: Whatever terminates a bus transaction whether it is normal or bus error. Note that bus cycles that result from a burst inhibited transfer are considered part of that original transfer. Freescale Semiconductor, Inc... Table 6-11.
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Bus Operation Freescale Semiconductor, Inc. MCF5206e, BR, BD, and BG connect to the bus arbiter, allowing the bus arbiter to control use of the external bus by the MCF5206e. Freescale Semiconductor, Inc... The MCF5206e requests the bus from the external bus arbiter by asserting bus request (BR) whenever an internal bus request is pending (the ColdFire core requests an access). The MCF5206e continues to assert BR until after the start of the external bus transfer.
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Freescale Semiconductor, Inc. Bus Operation implicit and explicit bus ownership due to the bus lock bit being set then an internal bus request being generated. C1 C2 C3 C4 C5 C6 C7 C8 C9 CLK A[27:0] TRANSFER ATTRIBUTES TS Freescale Semiconductor, Inc... TA D[31:0] BR BG BD BUS LOCK BIT IMPLICIT OWNERSHIP EXTERNAL MASTER EXPLICIT OWNERSHIP MCF5206e Figure 6-38.
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Freescale Semiconductor, Inc. Bus Operation Freescale Semiconductor, Inc... When the bus has been removed from the MCF5206e, one of two situations can occur. In the first case, the bus lock bit in the SIMR is cleared and the MCF5206e has explicit ownership of the bus. When the external bus master negates BG, the MCF5206e completes the current transfer, then negates BD and three-states the address, data, TS, R/W, and SIZ signals after completing the current bus cycle.
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Freescale Semiconductor, Inc. Bus Operation Freescale Semiconductor, Inc... master of the external bus. Also during C4, the external arbiter removes the grant from the MCF5206e by negating bus grant (BG). Because the MCF5206e is the current bus master and the bus lock bit in the SIMR is set to 1, it continues to assert BD even after the current transfer has completed. The MCF5206e negates the bus lock bit in the SIMR during C8.
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Freescale Semiconductor, Inc. Bus Operation Table 6-12. MCF5206e Three-Wire Bus Arbitration Protocol Transition Conditions PRESENT STATE RESET Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Operation MCF5206e can assert memory control signals (i.e., CS[7:0], WE[3:0], RAS[1:0] or CAS[3:0]) TA and BR during this state. Freescale Semiconductor, Inc... The implicit ownership state indicates that the MCF5206e owns the bus because bus grant (BG) is asserted to it.
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Bus Operation Freescale Semiconductor, Inc. The MCF5206e registers the value of A[27:0], R/W, and SIZ[1:0] on the rising edge of CLK in which TS is asserted. NOTE Freescale Semiconductor, Inc... If the pins A[27:24]/CS[7:4]/WE[0:3] are not assigned to output address signals, a value of $0 is assigned internally to A[27:24]. Also, TT[1:0] and ATM are not examined during external master transfers.
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Freescale Semiconductor, Inc. Bus Operation Table 6-14. Signal Source During External Master Accesses MEMORY SPACE Chip Select DRAM Default Memory ADDRESS (DRIVEN BY) CONTROL SIGNALS TRANSFER ACKNOWLEDGE External Master CS[7:0], WE[3:0] MCF5206e: if EMAA in CSCR is set to 1 MCF5206e: if DCAR in DCCR is RAS[1:0], CAS[3:0], DRAMW MCF5206e set to 1 External Master MCF5206e: if EMAA in DMCR is set to 1 Freescale Semiconductor, Inc... 6.10.
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Bus Operation Freescale Semiconductor, Inc. EXTERNAL MASTER 1. SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD 4. ASSERT TS FOR ONE CLK CYCLE 1. Freescale Semiconductor, Inc... MCF5206e NEGATE TS 1. REGISTER THE DATA 2. RECOGNIZE THE TRANSFER IS DONE 1. REGISTER EXTERNAL MASTER A[27:0], R/W, SIZ[1:0] 1. DRIVE TA TO NEGATED STATE* 2. LOAD WAIT STATE COUNTER WITH APPROPRIATE COUNT VALUE 1.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-42 illustrates transfer acknowledge (TA) assertion by the MCF5206e during external master read transfers. C1 C2 C3 C4 CLK EM TS EM A[27:0] $ADDR Freescale Semiconductor, Inc... EM R/W EM SIZ[1:0] D[31:0] TA TEA ATA Figure 6-42. External Master Read Transfer Using MCF5206e Transfer Acknowledge Timing (No Wait States) Clock 1 (C1) The read cycle starts in C1.
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Bus Operation Freescale Semiconductor, Inc. state. During C3, the external master samples the level of TA and if TA is asserted, latches the data and terminates the transfer. If TA is negated, the external master continues to insert wait states instead of terminating the transfer. The external master must continue to sample TA on successive rising edges of CLK until it is asserted. Clock 4 (C4) During C4, the selected slave device drives the data bus to a high-impedence state.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-44 illustrates TA assertion by the MCF5206e during external master write transfers. C1 C2 C3 C4 CLK EM TS EM A[27:0] $ADDR EM R/W Freescale Semiconductor, Inc... EM SIZ[1:0] EM D[31:0] TA TEA ATA Figure 6-44. External Master Write Transfer Using MCF5206e TransferAcknowledge Timing (No Wait States) Clock 1 (C1) The write cycle starts in C1.
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Bus Operation Freescale Semiconductor, Inc. the transfer. If TA is negated, the external master continues to output the data and inserts wait states instead of terminating the transfer. The external master must continue to sample TA on successive rising edges of CLK until it is asserted. Clock 4 (C4) During C4, the external master places the data bus in a high-impedence state. The MCF5206e negates TA and drives TA to a high impedence state after the next rising edge of CLK. Freescale Semiconductor, Inc..
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Freescale Semiconductor, Inc. EXTERNAL MASTER Freescale Semiconductor, Inc... 1. MCF5206e Bus Operation SYSTEM DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO READ (R/W = 1) 3. DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE 4. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 1. REGISTER DATA 2. RECOGNIZE THE 1ST TRANSFER IS DONE 3. INCREMENT APPROPRIATE ADDRESS BITS BASED ON SIZ[1:0], A[3:0] AND PORT SIZE 1. REGISTER DATA 2. RECOGNIZE THE 2ND TRANSFER IS DONE 3.
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Bus Operation Freescale Semiconductor, Inc. Figure 6-46 illustrates TA assertion by the MCF5206e during external master bursting read transfers. C1 C2 C3 C4 C5 C6 C7 CLK Freescale Semiconductor, Inc... EM TS EM A[27:2] $ADDR EM A[1:0] $0 $1 $2 $3 EM R/W EM SIZ[1:0] $0 D[31:24] TA TEA ATA Figure 6-46. External Master Bursting Longword Read Transfer to an 8-Bit Port Using MCF5206e Transfer-Acknowledge Timing (No Wait States) Clock 1 (C1) The read cycle starts in C1.
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Freescale Semiconductor, Inc. Bus Operation Clock 3 (C3) At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set to 1 and the number of wait states is zero, the MCF5206e drives TA signal to the asserted state. During C3, the external master samples the level of TA. If TA is asserted, the external master latches the first byte of data from D[31:24]. If TA is negated, the external master continues to insert wait states instead of terminating the transfer.
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Bus Operation Freescale Semiconductor, Inc. of transfer acknowledge. For more information on chip select transfers or DRAM transfers, refer to Section 8 Chip Selects or to Section 10 DRAM Controller. NOTE Freescale Semiconductor, Inc... An external master cannot initiate a bursting write transfer for a chip select or default memory space where the burst-enable bit (BRST) in the Chip Select Control Register (CSCR) or the Default Memory Control Register (DMCR) is cleared.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... EXTERNAL MASTER MCF5206e 1. DRIVE ADDRESS ON A[27:0] 2. DRIVE R/W TO WRITE (R/W = 0) 3. DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE 4. ASSERT TS FOR ONE CLK CYCLE 1. NEGATE TS 2. DRIVE DATA ON THE APPROPRIATE BYTE LANES BASED ON SIZ[1:0], A[1:0] AND PORT SIZE 1. RECOGNIZE THE 1ST TRANSFER IS DONE 2. INCREMENT APPROPRIATE ADDRESS BITS BASED ON SIZ[1:0], A[3:0] AND PORT SIZE 3. RECOGNIZE THE 2ND TRANSFER IS DONE 2.
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Freescale Semiconductor, Inc. Bus Operation Figure 6-48 illustrates TA assertion by the MCF5206e during external master bursting write transfers. C1 C2 C3 C4 C5 CLK EM TS EM A[27:2] $ADDR Freescale Semiconductor, Inc... EM A[1] EM A[0] EM R/W EM SIZ[1:0] $0 EM D[31:16] TA TEA ATA Figure 6-48. External Master Bursting Longword Write Transfer to a 16-Bit Port Using MCF5206e Transfer Acknowledge Timing (No Wait States) Clock 1 (C1) The write cycle starts in C1.
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Freescale Semiconductor, Inc. Bus Operation Clock 3 (C3) At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set to 1 and the number of wait states is zero, the MCF5206e asserts TA. During C3, the external master samples the level of TA. If TA is asserted, the transfer of the first word is complete. If TA is negated, the external master continues to insert wait states instead of terminating the transfer.
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Bus Operation Freescale Semiconductor, Inc. 6-49 is a functional timing diagram of the master reset operation, illustrating relationships among Vcc, RSTI, HIZ, RSTO, mode selects, and bus signals. CLK must be stable by the time Vcc reaches the minimum operating specification. CLK should start oscillating as Vcc is ramped up to clear out contention internal to the MCF5206e caused by the random manner in which internal flip-flops power up.
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Freescale Semiconductor, Inc. Bus Operation The levels of the IPLx pins select the port size and acknowledge features of the global chip select after a master reset occurs. The IPLx signals are synchronized and are registered on the last falling edge of CLK where RSTI and HIZ are asserted. Freescale Semiconductor, Inc... 6.11.2 NORMAL RESET External normal resets should be performed anytime it is important to maintain the data stored in DRAM during a reset.
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Bus Operation Freescale Semiconductor, Inc. bus signals continue to remain in a high-impedance state until the MCF5206e is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing. Freescale Semiconductor, Inc... A normal reset causes all bus activity except DRAM refresh cycles to terminate. During a normal reset, DRAM refresh cycles continues to occur at the programmed rate and with the programmed waveform timing.
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Freescale Semiconductor, Inc. Bus Operation and after the software watchdog timout reset at the programmed rate and with the programmed waveform timing. Freescale Semiconductor, Inc... TS must be pulled up or negated during software watchdog reset. When the software watchdog timeout recognized internally, the reset out pin (RTS2/RSTO) is asserted by the MCF5206e. RSTO is asserted for at least 31 CLK cycles after the internal software watchdog timer reset negated.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Bus Operation 6-86 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE SECTION 7 DMA CONTROLLER MODULE 7.1 INTRODUCTION Freescale Semiconductor, Inc... The Direct Memory Access Controller (DMA) Module provides a quick and efficient process for moving blocks of data with minimal processor overhead. The DMA module, shown in Figure 7-1, provides two channels that allow byte, word, or longword operand transfers. These transfers can be single or dual address to off-chip devices or dual address to on-chip devices.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. . EXTERNAL BUS CHANNEL 1 CHANNEL 0 EXTERNAL REQUESTS SAR SAR DAR DAR BCR BCR CNTRL CNTRL STATUS STATUS INTERRUPTS/ EXTERNAL BUS Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE • Data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer • Supports burst and cycle steal transfers • Independent transfer widths for source and destination • Independent source and destination address registers • Provide two clock data transfers 7.2 DMA SIGNAL DESCRIPTION This subsection contains a brief description of the DMA module signals used to provide handshake control for either a source or destination external device.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. Freescale Semiconductor, Inc... The DMA controller supports single- and dual-address transfers. In single-address mode, a channel supports 32 bits of address and 32 bits of data. Single-address transfers can be started by an external device using the request signal. The DMA provides address and control signals during a single-address transfer. The requesting device either sends or receives data to or from the specified address (see Figure 7-2).
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE DMA Freescale Semiconductor, Inc... MEMORY PERIPHERAL DMA MEMORY PERIPHERAL Figure 7-2. Single-Address Transfers MEMORY DMA MEMORY Figure 7-3. Dual-Address Transfers MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. 7.4 DMA CONTROLLER MODULE PROGRAMMING MODEL The registers of each DMA Controller Module channel are mapped into memory as shown in Figure 7-5. The base address for each channel of the DMA Controller Module is displayed in Table 7-7. Base Address Offset MBAR + DMA0SAR MBAR + DMA1SAR Channel Channel 0 Channel 1 Table 7-2. DMA Controller Module Channel Offsets Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE 7.4.2 Destination Address Register (DAR) The destination address register (DAR) is a 32-bit register containing the address to which the DMA Controller Module will send data during a transfer. Note that this register is only used during dual address transfers.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. 7.4.4 DMA Control Register The DMA control register (DCR) is a 16-bit register that controls the configuration of the DMA Controller Module. 15 14 13 12 INT EEXT CS AA 0 0 0 11 10 9 BWC 8 7 6 SAA S_RW SINC 0 0 0 5 4 SSIZE 3 2 DINC 1 DSIZE 0 START Reset: 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE BWC—Bandwidth Control These three bits are decoded to provide for internal bandwidth control. When the byte count has reached the programmed BWC boundary, the request signal to the internal arbiter is negated until the completion of the data access to enable the ColdFire core to access the bus.Table 7-8 shows the encodings for these bits. When the bits are cleared, the DMA does not negate its request.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. Table 7-4. SSIZE Encoding SSIZE 00 01 10 11 TRANSFER SIZE Longword Byte Word Line Freescale Semiconductor, Inc... DINC—Destination Increment This bit controls whether the destination address increments after each successful transfer. 1 = The DAR increments by 1, 2, 4, or 16 depending upon the size of the transfer. 0 = There is no change to the DAR after a successful transfer.
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE Bit 7—Reserved Freescale Semiconductor, Inc... CE—Configuration Error A configuration error results when either the number of bytes represented by the BCR is not consistent with the requested source or destination transfer size, or the SAR or DAR contains an address that does not match the requested transfer size for the source or destination, respectively. The bit is cleared during a hardware reset, or by writing a logic one to the DONE bit of the DSR.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. 7.4.6 DMA Interrupt Vector Register The DMA Interrupt Vector Register (DIVR) is an 8-bit register, which is sent to the ColdFire core in response to an acknowledge cycle. The register is selected when both the SMEN and SIVOE signals are asserted. 7 6 5 Reset: 0 0 0 4 3 Interrupt Vector Bits 0 1 2 1 0 1 1 1 DMA Interrupt Vector Register (DIVR) Freescale Semiconductor, Inc... 7.
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE last transfer before the boundary programmed in the BWC field. After the transfer is complete, it then asserts its internal bus request again to regain mastership at the earliest possible time as determined by the internal bus arbiter. The minimum amount of time that the DMA does not have the bus is one bus cycle. 7.6 DATA TRANSFER MODES Each DMA channel supports single- and dual-address transfers.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. 7.7 DMA CONTROLLER MODULE FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... In the following descriptions, “DMA request” implies that the START bit is set or the DREQ signal is asserted while the EEXT bit is set. The START bit is cleared when the channel begins an internal access.
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE loaded with the address of the peripheral data register. This address may be any byte address. In the single-address mode, this register is not used. The manner in which the SAR and DAR change after each cycle depends on the values in the DCR SSIZE and DSIZE fields and the SINC and DINC bits, and the starting address in the SAR and DAR.
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Freescale DMA CONTROLLER MODULE Semiconductor, Inc. NOTE: Freescale Semiconductor, Inc... You can DMA from on-chip serial ports using the UART interrupt signal as the source for external DMA requests (DREQ). The mechanism to accomplish this is to configure the Pin Assignment Register (PAR) bits 8 & 9 to the timer function. By doing this, the DMA external request line is sourced from the UART interrupts.
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Freescale Semiconductor, Inc. DMA CONTROLLER MODULE AA = 1, SAR = $0001, BCR = $00F0, SSIZE = 00 (longword) and DSIZE = 01 (byte), Because the SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on the destination registers.
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Semiconductor, Inc. Freescale Semiconductor, Inc... Freescale DMA CONTROLLER MODULE 7-18 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 1 2 SECTION 8 SYSTEM INTEGRATION MODULE 3 4 Freescale Semiconductor, Inc... 8.1 INTRODUCTION This subsection details the operation and programming model of the System Integration Module (SIM) registers, including the interrupt controller and system-protection functions for the MCF5206e. The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire® core processor and the internal peripherals or external devices.
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System Integration ModuleFreescale 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 14 15 Semiconductor, Inc. Family Programmer’s Reference Manual (MCF5200PRM/AD) for use of MOVEC instruction). The MBAR can be read when in debug mode using background debug commands. At system reset, the MBAR valid bit is cleared to prevent incorrect references to resources before the MBAR is written. The remainder of the MBAR bits are uninitialized.
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Freescale Semiconductor, Inc.System Integration Module 1 NOTE If an external device does not respond to an interrupt acknowledge cycle by asserting TA or ATA, an access error exception will be generated, not a spurious interrupt exception. To generate a spurious interrupt exception, TEA would have to be generated. 2 3 Freescale Semiconductor, Inc... 8.2.
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System Integration ModuleFreescale 1 2 All interrupt inputs are level sensitive. An interrupt request must be held valid for at least two consecutive CLK periods to be considered a valid input. The three external interrupt inputs can be programmed to be three individual interrupt inputs (at level 1, 4, and 7) or encoded interrupt priority levels.
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Freescale Semiconductor, Inc.System Integration Module The Software Watchdog Timer (SWT) has a fixed interrupt level (level 7). The interrupt priority of the SWT can be programmed to any value using the IP (IP1, IP0) bits in the SWT interrupt control register, ICR8. You cannot program the SWT to generate an autovector.The autovector bit in ICR8 is reserved and is always set to zero.
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System Integration ModuleFreescale 1 2 3 Semiconductor, Inc. You can assign as many as four interrupts to the same interrupt level, but you must assign unique interrupt priorities. The interrupt controller uses the interrupt priorities during an interrupt acknowledge cycle to determine which interrupt is being acknowledged.
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Freescale Semiconductor, Inc.System Integration Module • The access column indicates if the corresponding register allows both read/write functionality (R/W), read-only functionality (R), or write-only functionality (W). An attempted read access to a write-only register returns zeros. An attempted write access to a read-only register is ignored and no write occurs. Freescale Semiconductor, Inc... Table 8-2.
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System Integration ModuleFreescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.System Integration Module 1 • Operation of bus time-out monitor when the internal freeze signal is asserted • Operation of bus lock. The internal freeze signal is asserted when the core processor has entered into Background Debug mode (BDM) for software development purposes. The SIMR is an 8-bit read-write register. At system reset, FRZ1 and FRZ0 are set to 1 and BL is set to 0.
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System Integration ModuleFreescale 1 Table 8-3. Interrupt Control Register Assignments INTERRUPT SOURCE 2 4 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.System Integration Module IL[2:0] - Interrupt Level These bits indicate the interrupt level assigned to each interrupt input. Level 7 is the highest priority, level 1 is the lowest, and level 0 indicates that no interrupt is requested. For external interrupts and SWT, the corresponding IL2-IL0 are reserved bits. If the ICRs are programmed to have nonunique interrupt level and priority combination, unpredictable results could occur. 1 2 3 NOTE Freescale Semiconductor, Inc...
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System Integration ModuleFreescale 1 2 The IMR is a 16-bit read/write register. At system reset, all unreserved bits are initialized to one. Address MBAR + $36 Interrupt Mask Register(IMR) 15 3 Semiconductor, Inc. DMA 1 RESET: 0 14 13 12 11 10 9 DMA 0 UART 2 UART 1 MBUS TIMER 2 TIMER 1 0 1 1 1 1 8 7 6 5 4 3 2 1 0 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 - 1 1 1 1 1 1 1 1 0 1 R/W 4 Freescale Semiconductor, Inc... 5 8.3.2.
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Freescale Semiconductor, Inc.System Integration Module The IPR bit is cleared at the end of the interrupt acknowledge cycle. You cannot write to the IPR to clear any of the IPR bits. An active interrupt request appears as a set bit in the IPR, regardless of the setting of the corresponding mask bit in the IMR. Address MBAR + $3A Interrupt Pending Register (IPR) DMA 1 14 13 12 11 10 9 DMA 0 UART 2 UART 1 MBUS TIMER 2 TIMER 1 RESET: 0 0 0 0 2 3 The IPR is a 16-bit read-only register.
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System Integration ModuleFreescale 1 2 Semiconductor, Inc. The SYPCR is an 8-bit read-write register. The register can be read at anytime, but can be written only once after system reset. Subsequent writes to the SYPCR has no effect. At system reset, the software watchdog timer and the bus timeout monitor are disabled. System Protection Control Register(SYPCR) 3 7 6 5 SWE SWRI SWP 0 0 RESET: 0 4 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.System Integration Module 1 minimum timeout period. Freescale Semiconductor, Inc... Table 8-6.
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System Integration ModuleFreescale 1 The SWIVR is an 8-bit write-only register, which is set to the uninitialized vector $0F at system reset. 2 Freescale Semiconductor, Inc... 5 6 11 12 14 5 4 3 2 1 0 SWIV7 SWIV6 SWIV5 SWIV4 SWIV3 SWIV2 SWIV1 SWIV0 0 0 0 1 1 1 1 8.3.2.9 SOFTWARE WATCHDOG SERVICE REGISTER (SWSR). The SWSR is the location to which the SWT servicing sequence is written. To prevent an SWT timeout, you should write a $55 followed by a $AA to this register.
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Freescale Semiconductor, Inc.System Integration Module 1 PAR8 - Pin Assignment Bit 8 This bit lets you select the signal output on the TIN[0]/DREQ[0] pin as follows: 2 0 = Input Timer 0 (TIN[0]) signal on TIN[0]/DREQ[0] pin 1 = Input DMA channel 0 request on TIN[0]/DREQ[0] pin 3 PAR7 - Pin Assignment Bit 7 This bit lets you select the signal output on the RTS[2]/RSTO pin as follows: 4 Freescale Semiconductor, Inc...
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System Integration ModuleFreescale 1 Table 8-8. PAR3 - PAR0 Pin Assignment (Continued) 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 Semiconductor, Inc. PAR[3:0] A27/CS7/WE0 A26/CS6/WE1 A25/CS5/WE2 A24/CS4/WE3 0110 WE0 CS6 A25 A24 0111 WE0 A26 A25 A24 1000 CS7 CS6 CS5 CS4 1001 CS7 CS6 CS5 A24 1010 CS7 CS6 A25 A24 1011 CS7 A26 A25 A24 1100 A27 A26 A25 A24 1101 Reserved 1110 Reserved 1111 Reserved 8.9 BUS ARBITRATION CONTROL 8.9.
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Freescale Semiconductor, Inc.System Integration Module 1 set to the top priority if a higher priority master constantly demands the bus. Possible solutions to this problem are: • Changing the ARBCTRL setting at regular intervals to allow for different masters to share the highest priority. • Using lower priority masters for “non-essential” tasks which can be completed in the idle bus cycles of the top priority master. Freescale Semiconductor, Inc...
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System Integration ModuleFreescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 14 15 16 8-20 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. SECTION 9 CHIP SELECT MODULE 9.1 INTRODUCTION Freescale Semiconductor, Inc... The chip select module provides user-programmable control of the eight chip select and four write enable outputs. This subsection describes the operation and programming model of the chip select registers, including the chip select address, mask, and control registers. 9.1.
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Freescale Semiconductor, Inc. Chip Select Module During a write transfers, these outputs indicate which bytes within a long-word transfer are being selected and which bytes of the data bus are used for the transfer. WE[0] controls D[31:24], WE[1] controls D[23:16], WE[2] controls D[15:8] and WE[3] controls D[7:0].
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Freescale Semiconductor, Inc. Chip Select Module Table 9-1.
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Chip Select Module Freescale Semiconductor, Inc. Table 9-2. Maximum Memory Bank Sizes AVAILABLE ADDRESS SIGNALS MAXIMUM CS BANK SIZE A[23:0] A[24:0] A[25:0] A[26:0] A[27:0] 16 Mbyte 32 Mbyte 64 Mbyte 128 Mbyte 256 Mbyte Freescale Semiconductor, Inc... connected to external memory. The MCF5206e does not output the address during external master initiated transfers to chip select memory. 9.2.1.4 DATA BUS. You can configure the chip select and default memory spaces to be 8-, 16-, or 32-bits wide.
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Freescale Semiconductor, Inc. Chip Select Module interface to SRAM, EPROM, EEPROM and peripherals. Each of the eight chip select outputs has an address register, mask register and control register providing individual16bit address decode, 16-bit address masking, port size and burst capability indication, waitstate generation, automatic acknowledge generation as well as address setup and address hold features. Freescale Semiconductor, Inc... Chip selects 0 and 1 provide special functionality.
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Chip Select Module Freescale Semiconductor, Inc. looking for a match. The priority is listed in Table 9-3 (from highest priority to lowest priority): Table 9-3. Chip Select, DRAM and Default Memory Address Decoding Priority Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Chip Select Module • Address setup • Address hold • Enable read and/or write transfers Freescale Semiconductor, Inc... 9.3.1.3.1 8-, 16-, and 32-Bit Port Sizing. The general-purpose chip selects support static bus sizing. You can program the size of the port controlled by a chip select. Defined 8 bit ports are connected to D[31:24]; defined 16-bit ports are connected to D[31:16]; and defined 32 bit ports are connected to D[31:0].
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Chip Select Module Freescale Semiconductor, Inc. 9.3.1.3.4 Address Setup and Hold Control. The timing of the assertion and negation of the general-purpose chip selects and write enables can be programmed on a chip select basis. You can program each chip select to assert when the clock transfer start (TS) is asserted or assert the CLK cycle after transfer start (TS) is asserted. For burst transfers, you can select if the chip select remains valid while the burst address is incremented.
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Freescale Semiconductor, Inc. Chip Select Module 9.3.3.1 NONBURST TRANSFER WITH NO ADDRESS SETUP AND NO ADDRESS HOLD. Figure 9-2 illustrates a supervisor data longword write transfer to a 32-bit port. In this case, address setup and write address hold features are disabled. . C1 C2 CLK TS Freescale Semiconductor, Inc... A[27:0] $ADDR R/W TT[1:0] $0 ATM SIZ[1:0] $0 D[31:0] TA TEA ATA CS WE[3:0] Figure 9-2.
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Freescale Semiconductor, Inc. Chip Select Module Freescale Semiconductor, Inc... During C2, the MCF5206e negates transfer start (TS), drives access type and mode (ATM) high to identify the transfer as supervisor and drives data onto D[31:0]. If the selected device(s) is ready to latch the data, it latches D[31:0] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206e samples the level of TA.
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Freescale Semiconductor, Inc. Chip Select Module Clock 1 (C1) The write cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven low to identify the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer.
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Chip Select Module Freescale Semiconductor, Inc. . C1 C2 C3 C4 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $1 D[31:16] TA TEA ATA CS WE[0] WE[3:1] ADDRESS SETUP WAIT STATE ADDRESS HOLD Figure 9-4. Byte Write Transfer from an 8-Bit Port (One Wait State, Address Setup, Address Hold) Clock 1 (C1) The write cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Chip Select Module During C2, the MCF5206e negates transfer start (TS), drives access type and mode (ATM) high to identify if the transfer as supervisor, drives data onto D[31:16] and asserts the appropriate chip select (CS). At the end of C2, the MCF5206e samples the level of TA. If TA was asserted the transfer of the word would be complete. Since TA is negated, the MCF5206e continues to output the data and inserts a wait state instead of terminating the transfer.
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Freescale Semiconductor, Inc. Chip Select Module . C1 C2 C3 CLK TS A[27:0] $ADDR $ADDR + 2 R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $0 D[31:16] TA TEA ATA CS WE[3:0] Figure 9-5. Longword Burst Read Transfer from a 16-Bit Port (No Wait States, No Address Setup, No Address Hold) Clock 1 (C1) The burst read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Chip Select Module C2, the MCF5206e samples the level of TA and if TA is asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of the first word of the longword is complete. If TA is negated, the MCF5206e continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206e continues to sample TA on successive rising edge of CLK until it is asserted.
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Chip Select Module Freescale Semiconductor, Inc. . C1 C2 C3 C4 CLK TS A[27:0] $ADDR $ADDR + 2 R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $0 D[31:16] TA TEA ATA CS WE[3:0] ADDRESS SETUP ADDRESS SETUP Figure 9-6. Longword Burst Read Transfer from a 16-Bit Port (No Wait States, Address Setup, No Address Hold) Clock 1 (C1) The burst read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Chip Select Module Freescale Semiconductor, Inc... Clock 2 (C2) During C2, the MCF5206e negates transfer start (TS), drives access type and mode (ATM) low to identify if the transfer as user. The appropriate chip select (CS) signal is asserted. The selected device(s) places the addressed data onto D[31:16] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206e samples the level of TA and if TA is asserted, latches the current value of D[31:16].
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Freescale Semiconductor, Inc. Chip Select Module . C1 C2 C3 C4 C5 C6 CLK TS A[27:0] $ADDR $ADDR + 1 R/W Freescale Semiconductor, Inc... TT[1:0] $0 ATM SIZ[1:0] $2 D[31:24] TA TEA ATA CS WE[3:0] ADDRESS SETUP ADDRESS HOLD Figure 9-7. Word Burst Read Transfer from an 8-Bit Port (No Wait States, Address Setup, Address Hold) Clock 1 (C1) The burst read cycle starts in C1. During C1, the MCF5206e places valid values on the address bus (A[27:0]) and transfer control signals.
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Freescale Semiconductor, Inc. Chip Select Module Freescale Semiconductor, Inc... Clock 2 (C2) During C2, the MCF5206e negates transfer start (TS), drives access type and mode (ATM) high to identify the transfer as supervisor. The appropriate chip select (CS) signal is asserted. The selected device(s) places the addressed data onto D[31:24] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206e samples the level of TA and if TA is asserted, latches the current value of D[31:24].
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Chip Select Module Freescale Semiconductor, Inc. 9.3.4 External Master Chip Select Operation The MCF5206e can monitor bus transfers by other bus masters and assert chip select and transfer termination signals during these transfers. Assertion of chip select and termination signals occurs when the bus is granted to another bus master and TS is asserted by the external master as an input to the MCF5206e.
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Freescale Semiconductor, Inc. Chip Select Module . C1 C2 C3 C4 CLK TS A[27:0] $ADDR R/W Freescale Semiconductor, Inc... SIZ[1:0] $0 D[31:0] TA TEA ATA CS WE[3:0] Figure 9-8. External Master Longword Read Transfer from a 32-Bit Port (No Wait State, No Address Setup, No Address Hold) Clock 1 (C1) The write cycle starts in C1. During C1, the external master places valid values on the address bus (A[27:0]) and transfer control signals.
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Chip Select Module Freescale Semiconductor, Inc. complete. If TA is negated, the external master continues to sample TA and inserts wait states instead of terminating the transfer. Clock 4 (C4) Freescale Semiconductor, Inc... At the start of clock 4, the MCF5206e negates CS and TA, completing the external master transfer. After the next rising edge of CLK, the MCF5206e three states TA. The external master can assert TS starting another transfer. 9.3.4.2 EXTERNAL MASTER BURST TRANSFER.
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Freescale Semiconductor, Inc. Chip Select Module . C1 C2 C3 C4 C5 CLK TS A[27:0] $ADDR $ADDR + 2 R/W Freescale Semiconductor, Inc... SIZ[1:0] $0 D[31:16] TA TEA ATA CS WE[3:0] Figure 9-9. External Master Longword Read Transfer from a 16-bit Port (No Wait State, No Address Setup, No Address Hold) Clock 1 (C1) The read cycle starts in C1. During C1, the external master places valid values on the address bus (A[27:0]) and transfer control signals.
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Chip Select Module Freescale Semiconductor, Inc. transfer of the first word of the longword is complete. If TA is negated, the external master continues to sample TA and inserts wait states instead of terminating the transfer. Clock 4 (C4) At the start of clock 4, the external master increments the address to indicate the second word of the longword transfer. The MCF5206e continues to assert CS and TA and the selected slave outputs the data indicated by the new address on D[31:16].
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Freescale Semiconductor, Inc. Chip Select Module . C1 C2 C3 C4 C5 CLK TS A[27:0] $ADDR $ADDR + 2 R/W Freescale Semiconductor, Inc... SIZ[1:0] $0 D[31:16] TA TEA ATA CS WE[3:0] Figure 9-10. External Master Longword Read Transfer from a 16-Bit Port (No Wait State, With Address Setup Or Read Address Hold) Clock 1 (C1) The read cycle starts in C1. During C1, the external master places valid values on the address bus (A[27:0]) and transfer control signals.
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Chip Select Module Freescale Semiconductor, Inc. transfer of the first word of the longword is complete. If TA is negated, the external master continues to sample TA and inserts wait states instead of terminating the transfer. Clock 4 (C4) At the start of clock 4, the external master increments the address to indicate the second word of the longword transfer. The MCF5206e negates CS and TA. Freescale Semiconductor, Inc... Clock 5 (C5) At the start of clock 5, the MCF5206e asserts CS and TA.
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Freescale Semiconductor, Inc. Chip Select Module Freescale Semiconductor, Inc... Table 9-4.
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Freescale Semiconductor, Inc. Chip Select Module Table 9-4. Memory Map of Chip Select Registers (Continued) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Chip Select Module BA31-BA16 - Base Address This field defines the base address location of memory dedicated to each chip select. These bits are compared to ColdFire core address bus bits 31-16 to determine if the chip select memory is being accessed. During external master accesses these bits are compared as shown in Table 9-5. Table 9-5.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Chip Select Module For each transfer mask bit: 0 = Do not mask this type of transfer for the chip select. A transfer of this type can occur for this chip select. 1 = Mask this type of transfer from the chip select. If this type of transfer is generated, this chip select activation is not activated. NOTE Freescale Semiconductor, Inc... The C/I, SC, SD, UC, and UD bits are ignored during external master transfers.
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Freescale Semiconductor, Inc. Chip Select Module Table 9-6. IRQ4 and IRQ1 Selection of CS[0] Port Size IRQ4 IRQ1 BOOT CS[0] PORT SIZE 0 0 32-bit port 0 1 8-bit port 1 0 16-bit port 1 1 16-bit port Freescale Semiconductor, Inc... Table 9-7.
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Freescale Semiconductor, Inc. Chip Select Module BRST - Burst Enable This field specifies the burst capability of the memory associated with each chip select. Freescale Semiconductor, Inc... 0 = Break all transfers that are larger than the specified port size into individual nonburst transfers that are no larger than the specified port size (e.g.
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Chip Select Module Freescale Semiconductor, Inc. ASET - Address Setup Enable This field controls the assertion of chip select with respect to assertion of a valid address. 0 = Assert chip select on the rising edge of CLK that address is asserted. See Figure 9-11. 1 = Delay assertion of chip select for one CLK cycle after address is asserted. See Figure 9-12. CLK Freescale Semiconductor, Inc... TS ADDR CS WE Figure 9-11.
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Freescale Semiconductor, Inc. Chip Select Module 0 = Do not hold address, data, and attribute signals an extra cycle after CS and WE negate on writes. See Figure 9-13. 1 = Hold address, data, and attribute signals one cycle after CS and WE negate on writes. See Figure 9-14. Address Hold Timing with WRAH = 1. CLK TS Freescale Semiconductor, Inc... ADDR DATA ATTR R/W CS WE TA Figure 9-13. Address Hold Timing with WRAH = 0 CLK TS ADDR DATA ATTR R/W CS WE TA Figure 9-14.
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Freescale Semiconductor, Inc. Chip Select Module RDAH - Read Address Hold Enable This field controls the address and attribute hold time after the termination (TA, ATA, TEA or internal transfer acknowledge) during a read cycle that hits in the chip select address space. 0 = Do not hold address and attributes an extra cycle after CS negates on reads. See Figure 9-15. 1 = Hold address and attributes one cycle after CS negates on reads. See Figure 9-16. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Chip Select Module CLK TS ADDR DATA ATTR Freescale Semiconductor, Inc... R/W CS WE TA Figure 9-16. Address Hold Timing with RDAH = 1 WR - Write Enable This field controls the assertion of chip select and write enable on write cycles. 0 = Disable this chip select during write transfers 1 = Chip select and write enables assert on writes that hit in the chip select address space RD - Read Enable This field controls the assertion of chip select on read cycles.
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Freescale Semiconductor, Inc. Chip Select Module Default Memory Control Register(DMCR) Address MBAR + $C6 15 14 13 12 11 10 9 8 7 6 5 4 - - WS3 WS2 WS1 WS0 BRST AA PS1 PS0 EMAA - 0 0 0 0 0 0 0 0 0 0 0 RESET: 0 3 2 WRAH RDAH 0 0 1 0 - - 0 0 Freescale Semiconductor, Inc... WS[3:0] - Wait States On accesses initiated by the ColdFire core when AA=1, this field defines the number of wait states inserted before an internal transfer acknowledge is generated.
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Freescale Semiconductor, Inc. Chip Select Module outside of the chip select and DRAM address spaces, set AA to 0 in the DMCR and enable the Bus Timeout Monitor. PS[1:0] - Port Size This field specifies the width of the data associated with the default memory space. It determines which byte lanes are driven with valid data during write cycles and which byte lanes are sampled for valid data during read cycles. Freescale Semiconductor, Inc... Table 9-8.
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Freescale Semiconductor, Inc. Chip Select Module Bus Timeout Monitor does not monitor external master initiated transfers. WRAH - Write Address Hold Enable This field controls the address, data and attribute hold time after the termination (TA, ATA, TEA, or internal transfer acknowledge) of a write cycle that hits in the default memory address space. Freescale Semiconductor, Inc... 0 = Do not hold address extra cycle after the transfer is terminated on writes. See Figure 9-11.
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Freescale Semiconductor, Inc. Chip Select Module . CLK TS ADDR DATA ATTR Freescale Semiconductor, Inc... R/W CS WE TA Figure 9-18. Default Memory Address Hold Timing with WRAH = 1 RDAH - Read Address Hold Enable This field controls the address hold time after the termination (TA, ATA, TEA, or internal transfer acknowledge) of a read cycle that hits in the default memory address space. 0 = Do not hold address extra cycle after the transfer is terminated on reads. See Figure 9-12.
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Freescale Semiconductor, Inc. Chip Select Module CLK TS ADDR DATA ATTR Freescale Semiconductor, Inc... R/W CS WE TA Figure 9-19. Default Memory Address Hold Timing with RDAH = 0 CLK TS ADDR DATA ATTR R/W CS WE TA Figure 9-20. Default Memory Address Hold Timing with RDAH = 1 9-42 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Chip Select Module Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chip Select Module 9-44 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 1 2 SECTION 10 PARALLEL PORT (GENERAL-PURPOSE I/O) MODULE 4 10.1 INTRODUCTION The MCF5206e provides eight general-purpose input/output signals that can be used on a pin-by-pin basis. This subsection describes the operation and programming model of the parallel port registers and the direction-control and data registers. Freescale Semiconductor, Inc... 3 10.
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Freescale Parallel Port (General-Purpose I/O) Module Semiconductor, 1 2 3 4 10.3.2 Parallel Port Registers 10.3.2.1 PORT A DATA DIRECTION REGISTER (PADDR). The data direction register allows you to select the signal direction of each parallel port signal. There is one DDR bit in the PADDR for each parallel port signal. The data direction control bits will only affect the direction of the associated pin if you program that pin as a general- purpose I/O signal in the Pin Assigment Register (PAR).
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Freescale Semiconductor, Inc. Parallel Port (General-Purpose I/O) Module The Parallel Port Data Register is an 8-bit read/write register. At system reset, the PADAT is initialized to zeros. Parallel Port Data Register(PPDAT) 6 5 4 3 2 1 0 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 0 0 0 0 0 0 0 RESET: 0 2 Address MBAR + $1C9 7 1 3 R/W 4 Freescale Semiconductor, Inc... NOTE Bits in PADAT are valid for the pins configured as generalpurpose I/O only.
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Freescale Parallel Port (General-Purpose I/O) Module Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 9 10 11 12 13 14 15 16 10-4 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 1 SECTION 11 DRAM CONTROLLER 4 Freescale Semiconductor, Inc... 11.1 INTRODUCTION The DRAM controller (DRAMC) provides a glueless interface between the ColdFire® core and external DRAM. The DRAMC supports two banks of DRAM. Each DRAM bank can be from 128 KByte to 256 MByte. The DRAMC can support DRAM bank widths of 8, 16, or 32 bits. Two row address strobe (RAS[1:0]) signals are provided externally to access the two DRAM banks.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 11.2.1.2 COLUMN ADDRESS STROBES (CAS[0], CAS[1], CAS[2], CAS[3]). These active-low output signals provide control for the column address strobe (CAS) input pins on industry-standard DRAMs. The CAS signals are used to enable data byte lanes: CAS[0] controls access to D[31:24], CAS[1] to D[23:16], CAS[2] to D[15:8], and CAS[3] to D[7:0].
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Freescale Semiconductor, Inc. DRAM Controller 1 Table 11-1. CAS Assertion (Continued) CAS[0] OPERAND SIZE PORT SIZE 8-BIT SIZ[1] 1 SIZ[0] Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 2 3 11.2.3 Data Bus The DRAM banks can be configured to be 8, 16, or a 32-bits wide. A 32-bit port must reside on data bus bits D[31:0], a 16-bit port must reside on data bus bits D[31:16] and an 8-bit port must reside on data bus bits D[31:24]. This requirement ensures that the MCF5206e correctly transfers valid data to 8, 16 and 32-bit ports. Figure 11-1 illustrates the connection of the data bus to 8-, 16-, and 32-bit ports.
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Freescale Semiconductor, Inc. DRAM Controller 1 NOTE Master Reset must be asserted for all power-on resets. Failure to assert Master Reset on power-on reset could result in unpredictable DRAMC behavior. 2 11.3.1.1 MASTER RESET. During a master reset all registers in the DRAMC are initialized to a known state and all DRAMC operation is halted. The DRAM refresh counter does not count and DRAM refresh cycles are not generated. Any DRAM transfer or refresh cycle in progress is immediately terminated.
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Freescale Semiconductor, Inc. DRAM Controller 1 2 3 4 Freescale Semiconductor, Inc... 5 6 DCAR1). The bits that are masked is determined by the value programmed in the BAM field in the DRAMC Mask Registers (DCMR0 - DCMR1). The masking of address bits is used to define the address space of the DRAM bank. Address bits that are masked are not used in the comparison with the transfer address.
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Freescale Semiconductor, Inc. DRAM Controller 1 looking for a match. The priority is listed in Table 11-4 (from highest priority to lowest priority): Table 11-4. Chip Select, DRAM and Default Memory Address Decoding Priority Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 2 Table 11-5. DRAM Bank Programming Example 2 DRAM BANK DCAR DCMR DCCR ADDRESS MATCH TRANSFER TYPE READ/WRITE 0 1 $0400 $0500 $00FE0006 $000E0000 $03 $01 $04xxxxxx $050xxxxx supervisor-only all transfer types read/write read-only 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 14 15 Refer to Section 11.4.2.4 DRAM Controller Mask Register (DRMR0 - DCMR1) and Section 11.4.2.
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Freescale Semiconductor, Inc. DRAM Controller 1 address pins (A[x]) in the following order: A[9] to DA[0], A[10] to DA[1], A[11] to DA[2], A[12] to DA[3], A[13] to DA[4], A[14] to DA[5], A[15] to DA[6], A[16] to DA[7], and A[17] to DA[8]. Freescale Semiconductor, Inc... When the ColdFire core initiates a transfer to an address location in the DRAM, the MCF5206e drives the internal transfer address IA[27:0] onto the MCF5206e address pins A[27:0] and asserts RAS.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 size (BPS). The shaded address pins in each PS/BPS configuration outputs the row address during the assertion of RAS and the column address during the assertion of CAS. These signals should be connected to the DRAM address inputs. The number of address signals used depends on the size of the DRAM. Because byte CAS signals (CAS[3:0]) are provided, A[0] is unnecessary for 16-bit DRAMs and A[1:0] are unnecessary for 32-bit DRAMs.
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Freescale Semiconductor, Inc. DRAM Controller 1 Table 11-6. 8-bit Port Size Address Multiplexing Configurations Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 Table 11-7. 16-bit Port Size Address Multiplexing Configurations 2 3 4 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 Table 11-8. 32-bit Port Size Address Multiplexing Configurations Freescale Semiconductor, Inc...
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DRAM Controller Freescale Semiconductor, Inc. 1 Table 11-9. Bank Page Size Versus Actual DRAM Page Size 2 BANK PAGE SIZE (BPS) 3 512 Bytes 4 1 KByte s 2 KBytes Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 For the 4 M x 8 DRAM, the DCCR and DCMR would be programmed as follows: DCCR: $57 (port size = 8 bits, page size = 1KByte, burst page mode, read/write) DCMR: $001E0000 (A[20:17] are masked => 4 MByte) Freescale Semiconductor, Inc...
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 is occurring and asserts RAS. The MCF5206e then drives the column address onto the same address pins and asserts CAS. When the cycle is complete, both RAS and CAS are negated. 11.3.3.1 NONBURST TRANSFER IN NORMAL MODE. A nonburst transfer to DRAM occurs when the operand size is the same or smaller than the DRAM port size (e.g.,longword transfer to a 32-bit port, or byte transfer to a 16-bit port).
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Freescale Semiconductor, Inc. DRAM Controller 1 . H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8 H9 2 CLK A[27:9] ROW COL ROW 3 COL RAS 4 CAS[0] 5 Freescale Semiconductor, Inc... DRAMW 6 D[31:24] TS 7 INTERNAL TA 8 Figure 11-5. Byte Read Transfers in Normal Mode with 8-bit DRAM 9 Clock H1 The first DRAM-read transfer starts in H1.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 Clock H3 The internal transfer acknowledge asserts to indicate that the current transfer is completed and the data on the D[31:24] will be registered on the next rising edge of CLK. Clock H4 The MCF5206e registers the read data driven by the DRAM and negates the internal transfer acknowledge, RAS and CAS[0], ending the first byte-read transfer. This begins the RAS precharge.
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Freescale Semiconductor, Inc. DRAM Controller 1 MCF5206e asserts TS only once. The start of the secondary transfers of a burst is delayed by the DRAMC until the programmed RAS precharge time is reached. The timing of burst reads and burst writes is identical in normal page mode, with the exception of when the DRAM drives data on reads and when the MCF5206e drives data on writes.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Clock H2 The MCF5206e negates TS, drives the column address on A[27:9], and begins driving the data on D[31:16] for the first word write of the longword burst. Clock L2 The MCF5206e asserts CAS[1:0] to indicate the column address is valid on the A[27:9]. Clock H3 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 11.3.4 Fast Page Mode Operation Freescale Semiconductor, Inc... Fast page mode operation allows faster successive transfers to locations in DRAM that have the same row address. All locations with the same row address are said to be on the same “page.” Successive transfers that have the same row address as the initial transfer are called “page hits,” while successive transfers with different row addresses are called “page misses.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 Figure 11-7 shows the timing of a word write transfer to an 8-bit port in fast page mode. H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 CLK 3 A[27:9] 4 COL COL RAS CAS[0] 5 Freescale Semiconductor, Inc... ROW DRAMW 6 D[31:24] 7 TS 8 INTERNAL TA 9 10 11 12 13 14 Figure 11-7. Word Write Transfer in Fast Page Mode with 8-Bit DRAM Clock H1 The first byte write transfer of the word burst starts in H1.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock H3 The internal transfer acknowledge asserts to indicate that the first byte transfer of the word burst will be completed on the next rising edge of CLK. Clock H4 3 The MCF5206e negates the internal transfer acknowledge, and CAS[0] ending the first byte write transfer of the word burst. At this point, the new page has been opened; therefore, the MCF5206e continues to assert RAS. The negation of CAS[0] begins the CAS precharge.
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Freescale Semiconductor, Inc. DRAM Controller 1 2 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 CLK 3 A[27:9] 4 COL COL RAS 5 Freescale Semiconductor, Inc... ROW CAS[3:0] DRAMW 6 D[31:0] 7 TS 8 9 INTERNAL TA Figure 11-8. Longword Read Transfer Followed by a Page Hit Longword Read Transfer in Fast Page Mode with 32-Bit DRAM 10 Clock H1 11 The longword read transfer starts in H1.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock H3 The internal transfer acknowledge asserts to indicate that the longword read transfer will be completed and that data on D[31:0] will be registered on the next rising edge of CLK. Clock H4 3 The MCF5206e negates the internal transfer acknowledge and CAS[3:0], ending the longword read transfer. At this point the new page has been opened; therefore, the MCF5206e continues to assert RAS. Once CAS[3:0] are negated the DRAM three-states D[31:0].
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Freescale Semiconductor, Inc. DRAM Controller 1 2 Figure 11-9 shows the timing of a page being opened by a word write transfer to a 16-bit port in Fast Page Mode. The first word write transfer is followed by a page-hit word write transfer. The timing of the page-hit write transfer is the same regardless of whether the page was opened by a burst read, burst write, nonburst read, or nonburst write transfer.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock L2 The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9]. 2 Freescale Semiconductor, Inc... Clock H3 The internal transfer acknowledge asserts to indicate that the word write transfer will be completed on the next rising edge of CLK. 3 Clock H4 4 The MCF5206e negates the internal transfer acknowledge and CAS[1:0], ending the first word write transfer.
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Freescale Semiconductor, Inc. DRAM Controller 1 2 3 4 Freescale Semiconductor, Inc... 5 6 in the same page, but can also decrease performance when successive transfers hit in different pages. In cases where a page is open in one bank and a transfer hits in the other bank, the transfer is not delayed because the second bank has already been precharged. The fastest possible page miss transfer in fast page mode requires 4 clocks.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock H1 The first DRAM read transfer starts in H1. During H1, the MCF5206e drives the row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $1 indicating a byte transfer, and asserts TS. 2 3 Clock L1 The MCF5206e asserts RAS to indicate the row address is valid on A[27:9]. 4 Clock H2 Freescale Semiconductor, Inc... The MCF5206e negates TS, and drives the column address on A[27:9].
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DRAM Controller Freescale Semiconductor, Inc. 1 2 The RAS precharge time has been met, so the MCF5206e asserts RAS is to indicate the row address is valid on A[27:9]. Clock H8 3 4 The MCF5206e negates TS, and drives the column address on A[27:9]. Clock L8 The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives data on D[31:24]. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 NOTE Fast page mode is not supported for external master DRAM transfers. A DRAM bank programmed for fast page mode, operates in fast page mode for ColdFire core initiated transfers, but operates in burst page mode for external master initiated transfers. 2 3 Figure 11-11 shows the effect of bus arbitration on the DRAM signals when the external bus is idle and a page is open in fast page mode.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 The MCF5206e asserts CAS to indicate the column address is valid on A[27:9]. Clock H3 The internal transfer acknowledge asserts to indicate that the current transfer will be completed on the next rising edge of CLK. Clock H4 The MCF5206e negates the internal transfer acknowledge and CAS, ending the transfer. At this point, a page has been opened; therefore, the MCF5206e continues to assert RAS.
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Freescale Semiconductor, Inc. DRAM Controller 1 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8 H9 L9 H10 L10 H11 2 CLK A[27:9] ROW COL COL ROW 3 COL RAS 4 CAS[1:0] 5 Freescale Semiconductor, Inc... DRAMW 6 D[31:16] TS 7 INTERNAL TA 8 Figure 11-12. Longword Write Transfer Followed by a Word Read Transfer in Burst Page Mode with 16-Bit DRAM 9 Clock H1 The first word write transfer of the longword burst starts in H1.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 Clock H3 The internal transfer acknowledge asserts to indicate that the first word transfer of the longword burst will be completed on the next rising edge of CLK. Clock H4 The MCF5206e negates the internal transfer acknowledge, and CAS[1:0], ending the first word write transfer of the longword burst. At this point, the new page has been opened; therefore, the MCF5206e continues to assert RAS.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock L9 The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives the data on D[31:16]. Clock H10 2 3 The internal transfer acknowledge asserts to indicate that the current transfer will be completed and the data on D[31:16] will be registered on the next rising edge of CLK. 4 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 2 Figure 11-13 shows the timing of a word read in Fast Page Mode followed by a page miss word read using 8-bit wide EDO DRAM (the EDO bit in the DCTR is set). H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8 H9 L9 H10 L10 H11 L11 CLK 3 A[27:9] ROW COL COL ROW COL 4 RAS Freescale Semiconductor, Inc... 5 6 7 CAS[0] DRAMW D[31:24] TS 8 9 10 INTERNAL TA Figure 11-13.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock H3 The internal transfer acknowledge asserts to indicate that the first byte read transfer of the word burst will be completed and the data on D[31:24] will be registered on the next rising edge of CLK. 3 Clock L3 With EDO DRAM, data is driven continuously on a read after the falling edge of CAS until the next falling edge of CAS or until the rising edge of RAS. This allows the MCF5206e to negate CAS[0] on L3 to allow more CAS precharge time.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 Clock H8 The ColdFire core initiated a DRAM transfer on the previous cycle that missed the open page. Therefore, the MCF5206e negates RAS, beginning the RAS precharge. Once the RAS precharge time has been reached, a transfer to a new page can start. Once RAS is negated, the EDO DRAM disables its output drivers and D[31:0] is three-stated. Clock H9 The byte read transfer to a new page starts in H9.
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Freescale Semiconductor, Inc. DRAM Controller 1 initiate a refresh cycle if a DRAM transfer is occurring when the internal refresh request is made. The DRAMC waits until the active DRAM transfer is complete and then initiates the DRAM refresh cycle. Refresh cycles occur immediately after the internal refresh request is made during idle bus cycles and during nonDRAM transfers.
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DRAM Controller Freescale Semiconductor, Inc. 1 NOTE 2 During a master reset, the DCCR is reset to $000 (giving the slowest refresh rate) and the DCTR is reset to $0000 (giving the fastest waveform timing). After a master reset, the initialization sequence should program the DRAMC Refresh Register (DCRR) and the DRAMC Timing Register (DCTR) such that refresh cycles are generated at the required rate and with the required timing for the DRAM in the system.
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Freescale Semiconductor, Inc. DRAM Controller 1 reached, the MCF5206e does not start driving the row address and assert RAS until the precharge time has been reached. Freescale Semiconductor, Inc... For external master DRAM transfers, the MCF5206e drives TA as an output. TA is asserted to signify the end of each transfer (or subtransfer in the case of a burst).
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Freescale Semiconductor, Inc. DRAM Controller 1 2 Figure 11-14 illustrates the timing of an external master DRAM byte read transfer followed by a byte write transfer to a 8-bit port in normal mode. H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8 H9 L9 H10 L10 H11 L11 CLK 3 A[27:0] ROWA COLA ROWA COLA 4 RAS Freescale Semiconductor, Inc... 5 6 7 CAS[0] DRAMW D[31:24] TS 8 9 R/W SIZ[1:0] $1 $1 TA 10 Figure 11-14.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock H3 The MCF5206e has determined that the external master transfer is a DRAM access, so the MCF5206e drives A[27:0] with the same value as was registered on the rising edge of H2. A[27:9] contains the DRAM row address. The MCF5206e also drives DRAMW high, indicating a DRAM read cycle. 2 3 Clock L3 4 The MCF5206e asserts RAS to indicate the row address is valid on A[27:9]. Freescale Semiconductor, Inc...
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Clock H8 The MCF5206e has determined that the external master transfer is a DRAM access, so the MCF5206e drives the A[27:0] with the same value as was registered on the rising edge of H2. A[27:9] contains the row address for the DRAM. The MCF5206e also drives DRAMW low, indicating a DRAM write cycle. Clock L8 The MCF5206e asserts RAS to indicate the row address is valid on A[27:9]. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 The fastest possible external master burst transfer in normal mode requires 5 clocks for the first transfer of the burst and 4 clocks for the secondary transfers (including a 1.5 clock RAS precharge time). You can program the DCTR to generate slower normal mode transfers. Figure 11-15 illustrates the timing of a external master longword write transfer to a 16-bit DRAM in normal mode.
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DRAM Controller Freescale Semiconductor, Inc. 1 in the correct byte lanes based on the data size and the port size of the DRAM, and must drive the data to meet the timing specifications of the DRAM. In this case, the external master should drive the write data on D[31:16]. 3 Clock H2 4 On the rising edge of CLK when TS is asserted, the MCF5206e registers the address and attribute signals. It internally decodes these signals and determines if the external master transfer is a DRAM access.
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Freescale Semiconductor, Inc. DRAM Controller 1 Clock H8 The MCF5206e internally increments and multiplexes the address and drives out the column address on A[27:9] for the second word transfer of the longword burst write. 2 Clock L8 3 Clock L8 is the same as Clock L4. The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9].
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Freescale Semiconductor, Inc. DRAM Controller 1 2 3 4 possible nonburst transfer in burst page mode requires 5 clocks. You can program the DCTR to generate slower burst-page-mode transfers. Figure 11-16 illustrates the timing of a word read transfer to an 8-bit DRAM in burst page mode. In burst page mode after the first byte transfer of the burst is complete, RAS remains asserted while CAS[0] and TA are negated and the column address of the second byte transfer of the burst is driven.
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Freescale Semiconductor, Inc. DRAM Controller 1 SIZ[1:0] to $2 indicating a word transfer, and asserting TS. These inputs to the MCF5206e must be set up with respect to the rising edge of CLK H2. 2 Clock H2 On the rising edge of CLK when TS is asserted, the MCF5206e registers the address and attribute signals. It internally decodes these signals and determines if the external master transfer is a DRAM access.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 Clock H7 The MCF5206e asserts the TA signal to indicate that the first byte read transfer of the burst will be completed and the read data will be valid on D[31:24] on the next rising edge of CLK. Clock H8 4 Freescale Semiconductor, Inc... 5 6 7 The MCF5206e negates RAS, CAS[0], and TA, and three-states A[27:0], ending the final byte read transfer of the burst.
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Freescale Semiconductor, Inc. DRAM Controller 1 • Addresses not assigned to a register and undefined register bits are reserved for future expansion. Write accesses to these reserved address spaces and reserved register bits have no effect; read accesses return zeros. 2 • The reset value column indicates the register initial value at master reset and normal reset. Certain registers are uninitialized upon reset—they may contain random values after reset. 3 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 2 3 RC11 - RC0 - Refresh Count This field controls the frequency of refresh requests. The value stored in this field is multiplied by 16 system clocks to determine the refresh period. The refresh period can range from 16 system clocks to 65,536 system clocks. An RC field value of all zeros corresponds to 65,536 system clocks. Any write to the DCRR forces a refresh cycle to occur.
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Freescale Semiconductor, Inc. DRAM Controller 1 control the CAS assertion and negation time during fast page mode and burst page mode transfers. Refer to Figure 11-21 for a timing diagram of EDO DRAM page mode transfers. Freescale Semiconductor, Inc...
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DRAM Controller Freescale Semiconductor, Inc. 1 2 CLK 3 TS A 4 DRAMW RAS 5 Freescale Semiconductor, Inc... CAS 6 D INTERNAL TA 7 RCD RSH CP CAS CP Figure 11-18. Fast Page Mode or Burst Page Mode DRAM Transfer Timing 8 CLK 9 TS 10 A DRAMW 11 RAS CAS 12 13 D internal TA RCD 14 15 16 RSH CP CAS CP Figure 11-19.
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Freescale Semiconductor, Inc. DRAM Controller 1 normal mode timing. Refer to Figures 11-19 and 11-21 for fast-page-mode and burstpage-mode timing. 2 For transfers in normal mode: 00 = RAS negates 1.5 system clocks after the assertion of CAS 01 = RAS negates 2.5 system clocks after the assertion of CAS 10 = RAS negates 3.5 system clocks after the assertion of CAS 11 = Reserved 3 4 Freescale Semiconductor, Inc...
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DRAM Controller Freescale Semiconductor, Inc. 1 2 CLK 3 TS A 4 DRAMW RAS 5 Freescale Semiconductor, Inc... CAS 6 D INTERNAL TA 7 8 9 10 CAS Figure 11-20. Fast Page Mode Page Hit and Page Miss DRAM Transfer Timing CAS - Column Address Strobe Time This field, together with the EDO field, controls the number of system clocks that CAS asserts on transfers once a page is open in fast page mode and burst page mode.
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Freescale Semiconductor, Inc. DRAM Controller 1 2 CLK TS 3 A DRAMW 4 RAS 5 Freescale Semiconductor, Inc... CAS D 6 INTERNAL TA RCD RSH CP CAS CP Figure 11-21. Fast Page Mode or Burst Page Mode EDO DRAM Transfer Timing CP - CAS Precharge Time This field, together with the EDO field, controls the number of system clocks that CAS is negated after a page mode transfer. This field controls CAS timing for fast page mode and burst page mode.
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Freescale Semiconductor, Inc. DRAM Controller 1 2 CLK 3 RAS CAS 4 DRAMW Freescale Semiconductor, Inc... 5 CSR where 6 NOTE The DCTR should not be written while an external master transfer is in progress. The DCTR should be programmed as part of the initialization sequence and external master DRAM transfers should not be attempted until it has been written. Failure to do so results in unpredictable operation. 8 10 11 RP Figure 11-22. CAS Before RAS Refresh Cycle Timing 7 9 tCNRN 1.
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Freescale Semiconductor, Inc. DRAM Controller 1 address bits as $0. In order for a bank to be accessible to an external master, the address bits that are unavailable to the external master must either be set to 0 in the DCAR or be masked in the DCMR. 2 11.4.2.4 DRAM CONTROLLER MASK REGISTER (DCMR0 - DCMR1). Each DCMR holds the address mask for each of the DRAM banks as well the definition of which types of transfers are allowed for the DRAM banks. Each DCMR is a 32-bit read/write control register.
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 For each transfer mask bit: 0 = Do not mask this type of transfer for the DRAM bank. A transfer of this type can access the DRAM bank. 1 = Mask this type of transfer for the DRAM bank. A transfer of this type cannot access the DRAM bank. NOTE 4 The SC, SD, UC, and UD bits are ignored during external master transfers. Therefore, an external master transfer can access the DRAM banks regardless of the transfer masks. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DRAM Controller 1 BPS - Bank Page Size This field defines the bank page size for each DRAM bank for fast page mode and burst page mode. 00 = 512 Byte page size 01 = 1 KByte page size 10 = 2 KByte page size 11 = Reserved 3 PM - Page Mode Select This field selects the type of DRAM transfers generated for each DRAM bank: normal mode, fast page mode, or burst-page-mode transfers. Freescale Semiconductor, Inc...
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DRAM Controller Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 from $00100000 - $001EFFFF. DRAM Controller Control Register 0 (DCCR0) is then written making DRAM bank 0 have a 32-bit port size, a 512 Byte bank page size, generate fast-page-mode transfers, and be enabled for both read transfers and write transfers.
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Freescale Semiconductor, Inc. UART Modules SECTION 12 UART MODULES The MCF5206e contains two universal asynchronous/synchronous receiver/transmitters (UARTs) that act independently. Each UART is clocked by the system clock, which eliminates the need for an external crystal. This section applies to both UARTs, which are identical. Refer to Section 12.4 for addressing differences. Each UART module, shown in Figure 12-1, consists of the following major functional areas: Freescale Semiconductor, Inc...
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UART Modules Freescale Semiconductor, Inc. 12.1 MODULE OVERVIEW The MCF5206e contains two independent UART modules. Features of each UART module include the following: • UART clocked by the system clock or external clock (TIN) • Full duplex asynchronous/synchronous receiver/transmitter channel • Quadruple-buffered receiver • Double-buffered transmitter Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules The receiver accepts serial data on the channel receiver serial data input (RxD); converts it to parallel format; checks for a start bit, stop bit, parity (if any), or any error condition; and transfers the assembled character onto the bus during read operations. The receiver can be polled or interrupt driven. Refer to Section 12.3.2.2 Receiver for additional information. 12.1.2 Baud-Rate Generator/Timer Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules muxed with RSTO at the pin. Their functionality is determined by programming the Pin Assignment Register (PAR) in the SIM. ADDRESS BUS FOUR-CHARACTER RECEIVEBUFFER RXD CONTROL LOGIC DATA TWO-CHARACTER TRANSMITBUFFER TXD CTS INPUT PORT RTS EXTERNAL INTERFACE SIGNALS CONTROL UARTMODULE INTERNAL BUS Freescale Semiconductor, Inc... INTERFACETO CPU INTERNAL OUTPUT PORT IRQ 16-BITTIMER/ BAUD RATE GENERATOR SYSTEMCLOCK TIN(EXTCLK) Figure 12-2.
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Freescale Semiconductor, Inc. UART Modules 12.3 OPERATION The following paragraphs describe the operation of the baud-rate generator, transmitter and receiver, and other operating modes of the UART module. Freescale Semiconductor, Inc... 12.3.1 Baud-Rate Generator/Timer The timer references made here relative to clocking the UART are different than the MCF5206e timer module that is integrated on the bus of the ColdFire core.
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UART Modules Freescale Semiconductor, Inc. 12.3.2 Transmitter and Receiver Operating Modes The functional block diagram of the transmitter and receiver, including command and operating registers, is shown in Figure 12-4. The following paragraphs describe these functions in reference to this diagram. For detailed register information, refer to subsection 12.4 Register Description and Programming. Freescale Semiconductor, Inc... 12.3.2.1 TRANSMITTER.
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Freescale Semiconductor, Inc. EXTERNAL INTERFACE UART SERIAL CHANNEL W UART COMMAND REGISTER (UCR) UART MODE REGISTER 1 (UMR1) R/W UART MODE REGISTER 2 (UMR2) R/W R Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules C1 IN TRANSMISSION TxD TRANSMITTER ENABLED C1 C2 C3 C4 BREAK C6 5 TxRDY Freescale Semiconductor, Inc... (SR[2]) (SR2) INTERNAL MODULE SELECT CS CTS Disable 7 Trans. W W W W C1 C2 C3 START BREAK 6 W W C4 STOP BREAK W W W C5 NOT TRANSMITTED C6 1 RTS2 MANUALLY ASSERTED BY BIT- SET COMMAND Notes: 1. Timing shown for UMR2[4]=1 2. Timing shown for UMR2[5]=1 NOTES: 3. 1. CN=Transmit TIMING SHOWN8-bit FOR character UMR2(4) = 1 4.
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Freescale Semiconductor, Inc. UART Modules Freescale Semiconductor, Inc... 12.3.2.2 RECEIVER. The receiver is enabled through the UCR located within the UART module. Functional timing information for the receiver is shown in Figure 12-6. The receiver looks for a high-to-low (mark-to-space) transition of the start bit on RxD.
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Freescale Semiconductor, Inc. UART Modules C2 C1 RxD C3 C4 C5 C6 C8 C7 C6, C7, C8 ARE LOST DUE TO RECEIVER DISABLED RECEIVER ENABLED Freescale Semiconductor, Inc... RxRDY (SR0) FFULL (SR1) 2 2.5 INTERNAL MODULE SELECT CS R R R R R R R R STATUS DATA STATUS DATA STATUS DATA STATUS DATA C2 C1 C3 C4 C5 LOST OVERRUN (SR4) 1 RTS (OP0) RESET BY COMMAND UOP1[0]=1 UOP(0) =1 NOTES: 1. Timing shown for UMR1[7]=1 NOTES: 2. Timing shown for UMR1[6]=0 2.5Timing 1.
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Freescale Semiconductor, Inc. UART Modules 12.3.2.3 FIFO STACK. The FIFO stack is used in the UART receiver buffer logic. The FIFO stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the RxD (refer to Figure 12-4). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple buffered.
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UART Modules Freescale Semiconductor, Inc. the receiver asserts RTS. Using this mode of operation prevents overrun errors by connecting the RTS to the CTS input of the transmitting device. To use the RTS signals on UART 2, you must set up the MCF5206e Pin Assignment Register (PAR) in the SIM to enable the corresponding I/O pins for these functions. If the FIFO stack contains characters and the receiver is disabled, the CPU can still read the characters in the FIFO.
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Freescale Semiconductor, Inc. UART Modules transmitter link is disabled. This mode is useful for testing remote channel receiver and transmitter operation. While in this mode, the receiver clocks the transmitter. Because the receiver is not active, the CPU cannot read received data. All status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received.
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UART Modules Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 12.3.4 Multidrop Mode You can program the UART to operate in a wakeup mode for multidrop or multiprocessor applications. Functional timing information for the multidrop mode is shown in Figure 128. You select the mode by setting bits 3 and 4 in UART mode register 1 (UMR1). This mode of operation connects the master station to several slave stations (maximum of 256).
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Freescale Semiconductor, Inc. MASTER STATION A/D A/D TxD ADDR 1 1 C0 UART Modules A/D ADDR 1 2 0 TRANSMITTER ENABLED Freescale Semiconductor, Inc...
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UART Modules Freescale Semiconductor, Inc. 12.3.5 Bus Operation This subsection describes the operation of the bus during read, write, and interruptacknowledge cycles to the UART module. All UART module registers must be accessed as bytes. Freescale Semiconductor, Inc... 12.3.5.1 READ CYCLES. The CPU with zero wait states accesses the UART module because the MCF5206e system clock is also used for the UART module. The UART module responds to reads with byte data on D[7:0].
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Freescale Semiconductor, Inc. UART Modules mnemonic for the bit. The values shown below the register description are the values of those register bits after a hardware reset. A value of U indicates that the bit value is unaffected by reset. The read/write status is shown in the last line. Freescale Semiconductor, Inc... Table 12-1.
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Freescale Semiconductor, Inc. UART Modules You can use this feature for flow control to prevent overrun in the receiver by using the RTS output to control the CTS input of the transmitting device. If both the receiver and transmitter are programmed for RTS control, RTS control is disabled for both because such a configuration is incorrect. See Section 12.4.1.2 Mode Register 2 (UMR2) for information on programming the transmitter RTS control. On UART 2, RTS is muxed.
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Freescale Semiconductor, Inc. UART Modules “Force parity low” means forcing a 0 parity bit. “Force parity high” forces a 1 parity bit. B/C1–B/C0 — Bits per Character These bits select the number of data bits per character to be transmitted. The character length listed in Table 12-3 does not include start, parity, or stop bits. Freescale Semiconductor, Inc... Table 12-3. B/Cx Control Bits B/C1 B/C0 BITS/CHARACTER 0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits 12.4.1.2 MODE REGISTER 2 (UMR2).
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UART Modules Freescale Semiconductor, Inc. 1. Program the UART for the automatic-reset mode: UMR2[5]=1 2. Enable the transmitter 3. Assert the transmitter request-to send control: UOP1[0]=1 4. Send the message 5. Disable the transmitter after the TxRDY bit but not the TxEMP bit in the USR becomes asserted. Freescale Semiconductor, Inc... The last character will be transmitted and the UOP0[0] bit will be set causing the transmitter request-to-send control to be negated.
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Freescale Semiconductor, Inc. UART Modules Freescale Semiconductor, Inc... Table 12-5. SBx Control Bits SB3 SB2 SB1 SB0 LENGTH 6-8 BITS LENGTH 5 BITS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.563 0.625 0.688 0.750 0.813 0.875 0.938 1.000 1.563 1.625 1.688 1.750 1.813 1.875 1.938 2.000 1.063 1.125 1.188 1.250 1.313 1.375 1.438 1.500 1.563 1.625 1.688 1.750 1.813 1.875 1.938 2.000 12.4.1.
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UART Modules Freescale Semiconductor, Inc. FE — Framing Error 1 = A stop bit was not detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. The bit is valid only when the RxRDY bit is set. 0 = No framing error has occurred. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules Freescale Semiconductor, Inc... TxEMP — Transmitter Empty 1 = The transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter-holding register awaiting transmission. 0 = The transmitter buffer is not empty. Either a character is currently being shifted out or the transmitter is disabled.
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UART Modules Freescale Semiconductor, Inc. 12.4.1.4 CLOCK-SELECT REGISTER (UCSR). The UCSR selects the internal clock (timer mode) or the external clock in synchronous or asynchronous mode. To use the timer mode for either the receiver and transmitter channel, program the UCSR to the value $DD. The transmitter and receiver can be programmed to different clock sources.
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Freescale Semiconductor, Inc. UART Modules MISC3–MISC0 — Miscellaneous Commands These bits select a single command as listed in Table 12-8. Freescale Semiconductor, Inc... Table 12-8.
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UART Modules Freescale Semiconductor, Inc. Start Break The start break command forces TxD low. If the transmitter is empty, the start of the break conditions can be delayed by as much as two bit times. If the transmitter is active, the break begins when transmission of the character is complete. If a character is in the transmitter shift register, the start of the break is delayed until the character is transmitted.
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Freescale Semiconductor, Inc. UART Modules Do Not Use Do not use this bit combination because the result is indeterminate. RC1–RC0 — Receiver Commands These bits select a single command as listed in Table 12-10. Freescale Semiconductor, Inc... Table 12-10. RCx Control Bits RC1 RC0 COMMAND 0 0 1 1 0 1 0 1 No Action Taken Receiver Enable Receiver Disable Do Not Use No Action Taken The ‘‘no action taken’’ command causes the receiver to stay in its current mode.
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Freescale Semiconductor, Inc. UART Modules while the receiver shifts and updates from the bottom of the stack when the shift register has been filled (see Figure 12-4). URB MBAR + $18C 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 1 1 1 1 1 1 1 RESET: 1 READ ONLY SUPERVISOR OR USER Freescale Semiconductor, Inc... RB7–RB0 — These bits contain the character in the receiver buffer. 12.4.1.7 TRANSMITTER BUFFER (UTB).
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Freescale Semiconductor, Inc. UART Modules Bits 7, 6, 5, 3, 2, 1 — Reserved by Motorola. Freescale Semiconductor, Inc... COS — Change-of-State 1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25– 50 µs has occurred at the CTS input. When this bit is set, you can program the UART Auxiliary Control Register (UACR) to generate an interrupt to the CPU. 0 = No change-of-state has occurred since the last time the CPU read the UART Input Port Change Register (UIPCR).
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Freescale Semiconductor, Inc. UART Modules NOTE The UIMR does not mask reading of the UISR. True status is provided regardless of the contents of UIMR. A UART module reset clears the contents of UISR. UISR MBAR + $194 7 6 5 4 3 2 COS — — — — DB 0 0 0 0 1 0 RXRDY TXRDY RESET: 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules the state of the bit in the UISR has no effect on the interrupt output. The UIMR does not mask the reading of the UISR. UIMR MBAR + $194 7 6 5 4 3 2 1 0 COS — — — — DB FFULL TXRDY 0 0 0 0 0 0 0 RESET: 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules IVR7–IVR0 — Interrupt Vector Bits This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The UIVR is reset to $0F, which indicates an uninitialized interrupt condition. 12.4.1.14.1 Input Port Register (UIP). The UIP register shows the current state of the CTS input. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules Bit Reset UOP0 MBAR + $1BC 7 6 5 4 3 2 1 0 — — — — — — — RTS — — — — — — — RESET: — WRITE ONLY SUPERVISOR OR USER Freescale Semiconductor, Inc... RTS — Output Port Parallel Output 1 = A write cycle to the OP bit reset address negates RTS. 0 = This bit is not affected by writing a zero to this address. 12.4.2 Programming Figure 11-9 shows the basic interface software flowchart required for operation of the UART module.
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UART Modules Freescale Semiconductor, Inc. 12.5 UART MODULE INITIALIZATION SEQUENCE The following steps are required to properly initialize the UART module: Command Register (UCR) 1. Reset the receiver and transmitter. 2. Program the vector number for a UART module interrupt. However, if the UART Interrupt Control Register (ICR_U1) is programmed to generate an autovector, the UART Interrupt Vector Register (UIVR) must be programmed with an autovector number. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules ENABLA ENABLE SERIAL MODULE SINIT ANY ERRORS ? INITIATE: Y N CHANNEL INTERRUPTS Freescale Semiconductor, Inc... ENABLE RECEIVER CHK1 CALL CHCHK SAVE CHANNEL STATUS ASSERT REQUEST TO SEND SINITR RETURN Figure 11-9. UART Software Flowchart (1 of 5) MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. UART Modules CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE (NOTE: IN LOOPBACK MODE TRANSMITTER MUST BE ENABLED, NOT RECEIVER) Freescale Semiconductor, Inc... ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK N IS TRANSMITTER READY ? N Y WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG Y SET RECEIVERNEVER-READY FLAG N Y SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK N HAS CHARACTER BEEN RECEIVED ? N WAITED TOO LONG ? Y A B Figure 11-9.
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Freescale Semiconductor, Inc. B A FRCHK RSTCHN HAVE FRAMING ERROR ? N Y DISABLE TRANSMITTER RESTORE TO ORIGINAL MODE SET FRAMING ERROR FLAG PRCHK Freescale Semiconductor, Inc... UART Modules RETURN HAVE PARITY ERROR ? N Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER ? Y N SET INCORRECT CHARACTER FLAG B MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. UART Modules INCH SIRQ ABRKI WAS IRQ CAUSED BY BEGINNING OF A BREAK ? Y N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? N Y PLACE CHARACTER IN D0 CLEAR CHANGE-INBREAK STATUS BIT Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. UART Modules OUTCH IS TRANSMITTER READY ? N Y Freescale Semiconductor, Inc... SEND CHARACTER TO TRANSMITTER RETURN Figure 11-9. UART Software Flowchart (5 of 5) MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... UART Modules 12-40 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 1 2 SECTION 13 M-BUS MODULE 4 13.1 OVERVIEW Freescale Semiconductor, Inc... Motorola bus (M-Bus) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is compatible with the widely used I2C bus standard1. This two-wire bus minimizes the interconnection between devices. 5 This bus is suitable for applications requiring occasional communications over a short distance between many devices.
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Freescale Semiconductor, Inc. M-Bus Module 1 A block diagram of the complete M-Bus Module is shown in Figure 13-1. 2 ADDR IRQ DATA REGISTERS AND COLDFIRE INTERFACE ADDR_DECODE DATA_MUX 4 5 Freescale Semiconductor, Inc... CTRL_REG FREQ_REG ADDR_REG DATA_REG STATUS_REG 6 7 INPUT SYNC IN/OUT DATA SHIFT REGISTER START, STOP, AND ARBITRATION CONTROL 8 9 CLOCK CONTROL ADDRESS COMPARE 10 11 SCL 12 13 14 15 SDA Figure 13-1. M-Bus Module Block Diagram 13.
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Freescale Semiconductor, Inc. M-Bus Module 1 NOTE For further information on M-Bus system configuration, protocol, and restrictions please refer to the Philip’s I2C Standard 2 13.4 M-BUS PROTOCOL Normally, a standard communication is composed of four parts: (1) START signal, (2) slave address transmission, (3) data transfer, and (4) STOP signal. They are described briefly in the following sections and illustrated in Figure 13-2. MSB Freescale Semiconductor, Inc...
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M-Bus Module 1 2 Freescale Semiconductor, Inc. In addition, if the MCF5206e is master, it must not transmit an address that is equal to its slave address. The MCF5206e cannot be master and slave at the same time. Only the slave with a calling address that matches the one transmitted by the master will responds by returning an acknowledge bit by pulling the SDA low at the 9th clock (see Figure 13-2). 13.4.
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Freescale Semiconductor, Inc. M-Bus Module immediately switch over to slave-receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets a status bit to indicate loss of arbitration. 1 2 Freescale Semiconductor, Inc... 13.4.7 Clock Synchronization Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus.
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M-Bus Module 1 2 Freescale Semiconductor, Inc. then release it. If the slave SCL low period is greater than the master SCL low period, the resulting SCL bus signal low period is stretched. 13.5 PROGRAMMING MODEL Five registers are used in the M-Bus interface and the internal configuration of these registers is discussed in the following paragraphs.The programmer’s model of the M-Bus interface is shown below in Table 13-1. Table 13-1. M-Bus Interface Programmer’s Model 4 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. M-Bus Module frequency. The serial bit clock frequency is equal to the CPU clock divided as shown in Table 13-2, which also shows the serial bit clock frequency for a 33 MHz internal operating frequency2. Note that the MFDR frequency value can be changed at any point in a program. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. M-Bus Module 1 13.5.3 M-Bus Control Register (MBCR) M-Bus Control Register (MBCR) 2 RESET 7 6 5 4 3 2 1 MEN MIEN MSTA MTX TXAK RSTA - 0 0 0 0 0 0 0 Read/Write 4 Freescale Semiconductor, Inc... 7 8 9 10 11 12 13 14 0 0 Supervisor or User Mode MEN — M-Bus Enable This bit controls the software reset of the entire M-Bus module. 1 = The M-Bus module is enabled. This bit must be set before any other MBCR bits have any effect.
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Freescale Semiconductor, Inc. M-Bus Module Freescale Semiconductor, Inc... TXAK — Transmit Acknowledge Enable This bit specifies the value driven onto SDA during acknowledge cycles for both master and slave receivers. Note that writing this bit only applies when the M-Bus is a receiver, not a transmitter. 1 2 1 = No acknowledge signal response is sent (i.e.
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M-Bus Module 1 2 Freescale Semiconductor, Inc. MBB — Bus Busy Bit This bit indicates the status of the bus. When a START signal is detected, the MBB is set. If a STOP signal is detected, it is cleared. 1 = Bus is busy 0 = Bus is idle 5 1. SDA sampled as low when the master drives a high during an address or data-transmit cycle. Freescale Semiconductor, Inc... 4 MAL — Arbitration Lost Hardware sets the arbitration lost bit (MAL) when the arbitration procedure is lost.
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Freescale Semiconductor, Inc. M-Bus Module 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal has been detected at the 9th clock. 2 1 = No acknowledge received 0 = Acknowledge received 3 13.5.5 M-Bus Data I/O Register (MBDR) M-Bus Data I/O Register (MBDR) RESET Address MBAR+$1F0 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Read/Write Freescale Semiconductor, Inc...
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M-Bus Module 1 2 4 Freescale Semiconductor, Inc... 5 6 7 Freescale Semiconductor, Inc. M-Bus is busy after writing the calling address to the MBDR before proceeding with the following instructions. An example of a program that generates the START signal and transmits the first byte of data (slave address) is shown below: CHFLAGMOVE.BMBSR,-(A7); CHECK THE MBB BIT OF THE BTST.B#5, (A7)+ BNE.SCHFLAG; STATUS REGISTER. IF IT IS ; SET, WAIT UNTIL IT IS CLEAR TXSTARTMOVE.BMBCR,-(A7); SET TRANSMIT MODE BSET.
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Freescale Semiconductor, Inc. M-Bus Module 1 ISRLEA.LMBSR,-(A7); LOAD EFFECTIVE ADDR. BCLR.B#1,(A7)+; CLEAR THE MIF FLAG MOVE.BMBCR,-(A7); PUSH ADDRESS ON STACK, BTST.B#5,(A7)+; CHECK THE MSTA FLAG BEQ.SSLAVE; BRANCH IF SLAVE MODE MOVE.BMBCR,-(A7); PUSH ADDRESS ON STACK, BTST.B#4,(A7)+; CHECK THE MODE FLAG BEQ.SRECEIVE; BRANCH IF IN RECEIVE MODE MOVE.BMBSR,-(A7); PUSH ADDRESS ON STACK, BTST.B#0,(A7)+; CHECK ACK FROM RECEIVER BNE.B END; IF NO ACK, END OF TRANSMISSION TRANSMITMOVE.
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M-Bus Module 1 2 Freescale Semiconductor, Inc. ; TRANSMITTING BRANXMAR ENMASRBCLR.B#5,MBCR; LAST ONE, GENERATE'STOP' ; SIGNAL NXMARMOVE.BMBDR,RXBUF; READ DATA AND STORE RTE 13.6.5 Generation of Repeated START 4 RESTARTMOVE.BMBCR,-(A7); ANOTHER START (RESTART) BSET.B#2, (A7) MOVE.B(A7)+, MBCR MOVE.BCALLING,-(A7); TRANSMIT THE CALLING MOVE.BCALLING,-(A7); ADDRESS, D0=R/WMOVE.B(A7)+, MBDR Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. M-Bus Module the failed attempt to engage the bus. When considering these cases, the slave service routine should test the MAL first and the software should clear the MAL bit if it is set. 1 2 3 Freescale Semiconductor, Inc... 4 6 7 8 9 10 11 12 13 14 16 MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. M-Bus Module 1 2 CLEAR MIF Y MASTER MODE N ? 4 TX Y RX TX/RX ? ARBITRATION LOST ? N 5 LASTBYTE TRANSMITTED Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. 1 2 Freescale Semiconductor, Inc... SECTION 14 TIMER MODULE 3 14.1 OVERVIEW OF THE TIMER MODULE 4 The MCF5206e contains two general-purpose16-bit timers. This section of the manual documents how the 16-bit timers operate. 5 The output of an 8-bit prescaler clocks each 16-bit timer. The prescaler input can be the system clock, the system clock divided by 16, or the timer input (TIN) pin. Figure 14-1 is a block diagram of the timer module.
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Freescale Semiconductor, Inc. Timer Module 1 2 GENERAL-PURPOSE TIMER 3 7 0 EVENT REG 15 4 0 MODE REGISTER PRESCALER MODE BITS DIVIDER TIN CLOCK 15 0 BUS 5 Freescale Semiconductor, Inc... TIMER CLOCK GENERATOR TIMER COUNTER 6 15 CAPTURE DETECTION 0 REFERENCE REGISTER 7 SYSTEM CLOCK OR SYSTEM CLOCK/16 15 TOUT 0 CAPTURE REGISTER DATA BUS (16) IRQ 8 9 10 11 12 13 Figure 14-1. Timer Block Diagram Module Operation 14.
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Freescale Semiconductor, Inc. Timer Module 1 14.3.1 Selecting the Prescaler You can select the prescalar clock from the main clock (divided by 1 or by 16) or from the corresponding timer input TIN pin. TIN is synchronized to the internal clock. The synchronization delay is between two and three main clocks. TIN must meet the setup time spec shown in the AC Electrical Specs section. The ICLK bits of the corresponding Timer Mode Register (TMR) select the clock input source.
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Timer Module 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 14.4.1.1 TIMER MODE REGISTER (TMR). TMR is a 16-bit memory-mapped register. This register programs the various timer modes and is cleared by reset.
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Freescale Semiconductor, Inc. Timer Module RST — Reset Timer This bit performs a software timer reset identical to that of an external reset. All timer registers takes on their corresponding reset values. While this bit is zero, the other register values can still be written, if necessary. A transition of this bit from one to zero is what resets the register values. The counter/timer/prescaler is not clocked unless the timer is enabled. 2 3 1 = Enable timer 0 = Reset timer (software reset) 14.4.1.
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Timer Module 1 2 Freescale Semiconductor, Inc. 14.4.1.5 TIMER EVENT REGISTER (TER). The TER is an 8-bit register that reports events the timer recognizes. When the timer recognizes an event, it sets the appropriate bit in the TER, regardless of the corresponding interrupt-enable bits (ORI and CE) in the TMR. TER appears as a memory-mapped register and can be read at any time.
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Freescale Semiconductor, Inc. Timer Module 1 NOTE The timers were initialized in the SIM to have interrupt values. The examples below have the interrupts disabled. The initialization in the SIM configuration was for reference. The Timers CANNOT provide interrupt vectors, only autovectors. 2 3 Autovectors and ICRs have been set up as follows. The interrupt levels and priorities were chosen by random for demonstrative purposes.
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Timer Module 1 2 Timer 1 TMR register Bits 15:8 3 Freescale Semiconductor, Inc. sets the prescale to 256 ($FF) Bits 7:6 set for no interrupt ("00") Bits 5:4 sets output mode for "toggle". No interrupts("10") 4 5 Bits 3 set for "restart" ("1") Bits 2:1 set the clocking source to system clock/16 ("10") Freescale Semiconductor, Inc... Bit 0 enables/disables the timer 6 7 8 9 10 11 move.w move.w move.w to zero move.w #$FF2C,D0 D0,TMR1 ;; #$0000,D0 TRR1 register The TRR register is set to $AFAF.
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Freescale Semiconductor, Inc. Bit 1 enables the timer Timer Module 1 ("0") move.w move.w #$7F04,D0 D0,TMR2 ; ;Setup the Timer mode register (TMR2) move.w move.w #$1234,D0 D0,TRR2 ; ;Set the Timer reference to $1234 move.w move.w #$0000,D0 D0,TCN2 ; ;writing to the timer counter with any value resets it to zero 2 3 4 Freescale Semiconductor, Inc...
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Timer Module Freescale Semiconductor, Inc. 1 2 3 4 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 14 15 16 14-10 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. SECTION 15 DEBUG SUPPORT This section details the hardware debug support functions within the ColdFire® 5200 Family of processors. Freescale Semiconductor, Inc... The general topic of debug support is divided into three separate areas: 1. Real-Time Trace Support 2. Background Debug Mode (BDM) 3. Real-Time Debug Support Each of the three areas is addressed in detail in the following subsections.
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Freescale Semiconductor, Inc. Debug Support The processor status timing is synchronous with the processor clock (CLK) and the status may not be related to the current bus transfer. Table 15-1 below shows the encodings of these signals. Table 15-1. Processor PST Definition Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support a configurable parameter (2, 3, or 4 bytes). The nibble-wide DDATA port includes two 32-bit storage elements for capturing the CPU core bus information. These two elements effectively form a FIFO buffer connecting the core bus to the external development system. The FIFO buffer captures variant branch target addresses along with certain operand read/write data for eventual display on the DDATA output port.
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Debug Support Freescale Semiconductor, Inc. Additionally, a WDDATA opcode is supported that lets the processor core write any operand (byte, word, longword) directly to the DDATA port, independent of any Debug module configuration. This opcode also generates the special PST = $4 encoding when executed. 15.2 BACKGROUND DEBUG MODE (BDM) ColdFire 5200 processors support a modified version of the BDM functionality found on Motorola’s CPU32 Family of parts.
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Freescale Semiconductor, Inc. Debug Support 1. The occurrence of the catastrophic fault-on-fault condition automatically halts the processor. The halt status is posted on the PST port ($F). Freescale Semiconductor, Inc... 2. The occurrence of a hardware breakpoint (reference subsection Section 15.3 Realtime Debug Support) can be configured to generate a pending halt condition in a manner similar to the assertion of the BKPT signal.
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Freescale Semiconductor, Inc. Debug Support 15.2.2 BDM Serial Interface Once the CPU is halted and the halt status reflected on the PST outputs (PST[3:0]=$F), the development system can send unrestricted commands to the Debug module. The Debug module implements a synchronous protocol using a three-pin interface: development serial clock (DSCLK), development serial input (DSI), and development serial output (DSO).
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Freescale Semiconductor, Inc. Debug Support Debug module’s serial state machine are based on the rising edge of the microprocessor clock. Refer to Section 17: Electrical Characteristics. CLK DSCLK Freescale Semiconductor, Inc... DSI DSO Figure 15-4. BDM Signal Sampling The basic packet of information is a 17-bit word (16 data bits plus a status/control bit), as shown here.
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Debug Support Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 15.2.3.1 BDM COMMAND SET SUMMARY. The BDM command set is summarized in Table 15-3. Subsequent paragraphs contain detailed descriptions of each command. 15-8 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Debug Support Freescale Semiconductor, Inc... Table 15-3.
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Debug Support Freescale Semiconductor, Inc. Operand Size For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as listed in Table 15-4. Table 15-4. BDM Size Field Encoding Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support The “not ready” response is ignored unless a memory bus cycle is in progress. Otherwise, the debug module can accept a new serial transfer after eight system clock periods. In the third cycle, the development system supplies the low-order 16 bits of a memory address. The debug module always returns the “not ready” response in this cycle. At the completion of the third cycle, the debug module initiates a memory read operation.
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Freescale Semiconductor, Inc. Debug Support Note All the accompanying valid BDM results are defined with the most significant bit of the 17-bit response (S/C) as 0. Invalid command responses (Not Ready; TEA-terminated bus cycle; Illegal Command) return a 1 in the most significant bit of the 17bit response (S/C). Freescale Semiconductor, Inc... Motorola reserves unassigned command opcodes for future expansion.
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Freescale Semiconductor, Inc. Debug Support Command Formats: 15 14 13 12 11 10 $2 9 8 7 6 $0 5 4 $8 3 2 A/D 1 0 REGISTER DATA [31:16] DATA [15:0] WAREG/WDREG Command Command Sequence: Freescale Semiconductor, Inc... WDREG/WAREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX BERR NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Operand Data: Longword data is written into the specified address or data register. The data is supplied most significant word first.
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Freescale Semiconductor, Inc. Debug Support 15 14 13 12 11 10 $1 9 8 7 6 $9 5 4 3 2 $4 1 0 1 0 1 0 1 0 $0 ADDRESS [31:16] ADDRESS [15:0] Word READ Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 5 4 3 2 DATA [15:0] Word READ Result 15 14 13 12 11 10 $1 9 8 7 6 $9 $8 $0 ADDRESS [31:16] Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support bits of significant data; longword results return 32 bits. A successful read operation returns data bit 16 cleared. If a bus error is encountered, the returned data is $10001. 15.2.3.4.4 Write Memory Location (WRITE). Write the operand data to the memory location specified by the longword address. The address space is defined by the contents of the low-order 5 bits {TT, TM} of the address attribute register (AATR).
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Freescale Semiconductor, Inc. Debug Support Command Sequence: WRITE (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" DATA "NOT READY" WRITE MEMORY CONTROL MEMORY LOCATION REGISTER LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in ABHR. NOTE The DUMP command does not check for a valid address in ABHR—DUMP is a valid command only when preceded by another DUMP, NOP or by a READ command. Otherwise, an illegal command response is returned. The NOP command can be used for intercommand padding without corrupting the address pointer. Freescale Semiconductor, Inc...
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Debug Support Freescale Semiconductor, Inc. Command Sequence: DUMP (B/W) ??? READ MEMORY LOCATION XXX "NOT READY" NEXT CMD RESULT XXX "ILLEGAL" Freescale Semiconductor, Inc... DUMP (LONG) ??? NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "ILLEGAL" XXX BERR NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "NOT READY" NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD "NOT READY" Operand Data: None Result Data: Requested data is returned as either a word or longword.
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Freescale Semiconductor, Inc. Debug Support 15.2.3.4.6 Fill Memory Block (FILL). FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. The FILL command writes subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and is saved in ABHR after the memory write.
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Freescale Semiconductor, Inc. Debug Support Command Sequence: FILL(LONG) (B/W) ??? WRITE MEMORY LOCATION LS DATA "NOT READY" MS DATA "NOT READY" XXX "ILLEGAL" XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" NEXT CMD "NOT READY" Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support Command Sequence: GO ??? NEXT CMD "CMD COMPLETE" Freescale Semiconductor, Inc... Operand Data: None Result Data: The “command complete” response ($0FFFF) is returned during the next shift operation. 15.2.3.4.8 No Operation (NOP). NOP performs no operation and can be used as a null command, where required.
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Freescale Semiconductor, Inc. Debug Support Formats 15 14 13 12 11 10 9 $2 $9 $0 $0 8 7 6 $0 5 4 3 2 $8 $0 $0 $0 1 0 1 0 RC RCREG Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DATA [31:16] DATA [15:0] Freescale Semiconductor, Inc... RCREG Result Rc encoding: Table 15-5.
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Freescale Semiconductor, Inc. Debug Support of the longword are undefined. As an example, a read of the 16-bit SR returns the SR in the lower word and undefined data in the upper word. 15.2.3.4.10 Write Control Register (WCREG). The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Formats: 15 14 13 12 11 10 9 $2 $8 $0 $0 8 7 6 $0 5 4 3 2 1 $8 $0 $0 $0 0 Rc DATA [31:16] Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support Command Formats: 15 14 13 12 11 10 9 $2 8 7 6 $D 5 4 3 2 $8 1 0 1 0 DRc RDMREG BDM Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DATA [31:16] DATA [15:0] RDMREG BDM Result Freescale Semiconductor, Inc... DRc encoding: Table 15-6.
PAGE 431
Freescale Semiconductor, Inc. Debug Support Command Format: 15 14 13 12 11 10 $2 9 8 7 $C 6 5 4 3 2 $8 1 0 DRC DATA [31:16] DATA [15:0] WDMREG BDM Command DRc encoding: Table 15-7. Definition of DRc Encoding - Write Freescale Semiconductor, Inc...
PAGE 432
Debug Support Freescale Semiconductor, Inc. 15.3 REAL-TIME DEBUG SUPPORT ColdFire processors provide support for the debug of real-time applications. For these types of embedded systems, the processor cannot be halted during debug but must continue to operate. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can tolerate small intrusions into the real-time operation. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support sampling occurs. For the address and data breakpoints, the reporting is considered imprecise because several additional instructions may be executed after the triggering address or data is seen. Freescale Semiconductor, Inc... Once the debug interrupt is recognized, the processor aborts execution and initiates exception processing. At the initiation of the exception processing, the core enters emulator mode.
PAGE 434
Debug Support Freescale Semiconductor, Inc. 15.3.1.2 DEBUG MODULE HARDWARE. 15.3.1.2.1 Reuse of Debug Module Hardware. The Debug Module implementation provides a common hardware structure for both BDM and breakpoint functionality. Several structures are used for both BDM and breakpoint purposes. Table 15-9 identifies the shared hardware structures. Freescale Semiconductor, Inc... Table 15-9.
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Freescale Semiconductor, Inc. Debug Support NOTE When a BDM command is serially shifted into a ColdFire microprocessor, the debug module requests the use of the internal bus to perform the required operation. Under certain conditions, the processor may never grant the internal bus to the debug module causing the BDM command to never be performed. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Debug Support Control Registers (DRc), are addressed using a 4-bit value as part of two new BDM commands (WDREG, RDREG). Freescale Semiconductor, Inc... These registers are also accessible from the processor’s supervisor programming model through the execution of the WDEBUG instruction (Figure 15-5 illustrates the debug module programming model).
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Freescale Semiconductor, Inc. Debug Support R[7]–Read/Write This field is compared with the R/W signal of the processor’s local bus. SZ[6:5]—Size This field is compared to the size signals of the processor’s local bus. These signals indicate the data size for the bus transfer. Freescale Semiconductor, Inc... 00 = Longword 01 = Byte 10 = Word 11 = Reserved TT[4:3]—Transfer Type This field is compared with the transfer type signals of the processor’s local bus.
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Debug Support Freescale Semiconductor, Inc. The encoding for acknowledge/CPU space transfers (TT = 11) is: Freescale Semiconductor, Inc... 000 = CPU Space Access 001 = Interrupt Acknowledge Level 1 010 = Interrupt Acknowledge Level 2 011 = Interrupt Acknowledge Level 3 100 = Interrupt Acknowledge Level 4 101 = Interrupt Acknowledge Level 5 110 = Interrupt Acknowledge Level 6 111 = Interrupt Acknowledge Level 7 15.3.3.3 PROGRAM COUNTER BREAKPOINT REGISTER (PBR, PBMR).
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Freescale Semiconductor, Inc. BITS Debug Support 31 0 FIELD MASK RESET - R/W W Data Breakpoint Mask Register (DBMR) The data breakpoint register supports both aligned and misaligned operand references. The relationship between the processor core address, the access size, and the corresponding location within the 32-bit core data bus is shown in Table 15-12. Freescale Semiconductor, Inc... Table 15-10.
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Debug Support Freescale Semiconductor, Inc. trigger condition. The trigger response is always displayed on the DDATA pins. 00=displayed on DDATA pins only 01=processor halt 10=debug interrupt 11=reserved Freescale Semiconductor, Inc... EBL–Enable Breakpoint Level If set, this bit serves as the global enable for the breakpoint trigger. If cleared, all breakpoints are disabled.
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Freescale Semiconductor, Inc. Debug Support EAR–Enable Address Breakpoint Range If set, this bit enables the address breakpoint based on the inclusive range defined by ABLR and ABHR. EAL–Enable Address Breakpoint Low If set, this bit enables the address breakpoint based on the address contained in the ABLR. Freescale Semiconductor, Inc... EPC–Enable PC Breakpoint If set, this bit enables the PC breakpoint. Clearing this bit disables the PC breakpoint.
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Debug Support Freescale Semiconductor, Inc. DDATA[0] bit. 000x = no breakpoints enabled 001x = waiting for level 1 breakpoint 010x = level 1 breakpoint triggered 101x = waiting for level 2 breakpoint 110x = level 2 breakpoint triggered Freescale Semiconductor, Inc... This breakpoint status is also output on the DDATA port when the bus is not displaying ColdFire CPU core captured data. A write to the TDR resets this field.
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Freescale Semiconductor, Inc. Debug Support DDC–Debug Data Control This 2-bit field provides configuration control for capturing operand data for display on the DDATA port. The encoding is as follows: 00 = no operand data is displayed 01 = capture all internal write data 10 = capture all internal read data 11 = capture all internal read and write data Freescale Semiconductor, Inc... In all cases, the DDATA port displays the number of bytes defined by the operand reference size, i.e.
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Freescale Semiconductor, Inc. Debug Support 15.4 MOTOROLA RECOMMENDED BDM PINOUT Freescale Semiconductor, Inc... The ColdFire BDM connector is a 26-pin Berg connector arranged 2x13, shown in Figure 15-6.
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Freescale Semiconductor, Inc. Debug Support DSCLK DSI DSO 16 0 15 16 15 1 0 Freescale Semiconductor, Inc... Figure 15-8. Serial Transfer Illustration 15-39 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Debug Support 15-40 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 16 IEEE 1149.1 TEST ACCESS PORT (JTAG) The MCF5206e includes dedicated user-accessible test logic that is fully compliant with the IEEE standard 1149.1 Standard Test Access Port and Boundary Scan Architecture. Use the following description in conjunction with the supporting IEEE document listed above.
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IEEE 1149.1 Test Access Port (JTAG) Freescale Semiconductor, Inc. 16.1 OVERVIEW Figure 16-1 is a block diagram of the MCF5206e implementation of the 1149.1 IEEE Standard. The test logic includes several test data registers, an instruction register, instruction register control decode, and a 16-state dedicated TAP controller. TEST DATA REGISTERS BOUNDARY SCAN REGISTER V+ Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.Test Access Port (JTAG) IEEE 1149.1 When the compliance-enable is set for JTAG mode, the pin descriptions in Table 16-1 apply. Table 16-1.
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IEEE 1149.1 Test Access Port (JTAG) Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... also configure the direction of bidirectional pins and establish high-impedance states on some pins. The EXTEST instruction becomes active on the falling edge of TCK in the update-IR state when the data held in the instruction-shift register is equivalent to octal 0. 16.3.1.2 IDCODE. The IDCODE instruction selects the 32-bit IDcode register for connection as a shift path between the TDI pin and the TDO pin.
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Freescale Semiconductor, Inc.Test Access Port (JTAG) IEEE 1149.1 The HIGHZ instruction goes active on the falling edge of TCK in the update-IR state when the data held in the instruction shift register is equivalent to octal 5. Freescale Semiconductor, Inc... 16.3.1.5 CLAMP INSTRUCTION.
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IEEE 1149.1 Test Access Port (JTAG) Freescale Semiconductor, Inc. Bits 11-1 JEDEC ID Indicates the reduced JEDEC ID for Motorola (JEDEC refers to the Joint Electron Device Engineering Council. Refer to JEDEC publication 106-A and chapter 11 of the IEEE 1149.1 Standard for further information on this field). Bit 0 Differentiates this register as the JTAG IDcode register (as opposed to the bypass register) according to the IEEE 1149.1 Standard. Freescale Semiconductor, Inc... 16.3.
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Freescale Semiconductor, Inc.Test Access Port (JTAG) IEEE 1149.1 1 TEST - LOGIC - RESET TLR <-- VALUE OF TMS AT RISING EDGE OF TCK 0 RUN - TEST - IDLE 0 1 1 1 SELECT - DR - SCAN SELECT - IR - SCAN SeIR SeDR RTI 0 0 Freescale Semiconductor, Inc...
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IEEE 1149.1 Test Access Port (JTAG) Freescale Semiconductor, Inc. system clock which is not synchronized to TCK internally. Any mixed operation requiring the use of 1149.1 test logic in conjunction with system functional logic that uses both clocks must have coordination and synchronization of these clocks done externally to the MCF5206e. 16.6 DISABLING THE IEEE 1149.1 STANDARD OPERATION Freescale Semiconductor, Inc... There are two methods by which the MCF5206e can be used without the IEEE 1149.
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Freescale Semiconductor, Inc.Test Access Port (JTAG) IEEE 1149.1 TRST/DSCLK have internal pullups enabled. Figure 16-4 shows pin values recommended for disabling JTAG with the MCF5206e in Debug mode. VDD JTAG TDI /DSI DEBUG INTERFACE TMS/BKPT TRST/DSCLK Freescale Semiconductor, Inc... TCK Figure 16-4. Disabling JTAG in Debug Mode 16.7 MOTOROLA MCF5206E BSDL DESCRIPTION The MCF5206e BSDL description is available on the World Wide Web at http://www.mot.com/coldfire 16.8 OBTAINING THE IEEE 1149.
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Semiconductor, Inc. Freescale Semiconductor, Inc... IEEE 1149.1 Test Access Port (JTAG) Freescale 16-10 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
PAGE 457
Freescale Semiconductor, Inc. SECTION 17 ELECTRICAL CHARACTERISTICS 17.1 MAXIMUM RATINGS 17.1.1 Supply, Input Voltage and Storage Temperature Freescale Semiconductor, Inc... Table 17-1. Supply, Input Voltage and Storage Temperature RATING SYMBOL VALUE UNIT Supply voltage VDD -0.3 to + 4.0 V Maximum Operating Voltage VDD +3.6 V Minimum Operating Voltage VDD +3.0 V Input voltage Vin -0.5 to+5.
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Electrical Characteristics Freescale Semiconductor, Inc. 17.1.2 Operating Temperature Table 17-2. Operating Temperature SYMBOL VALUE UNIT Maximum operating junction temperature TJ TBD o Maximum operating ambient temperature TAmax 70a o Maximum operating ambient temperature (Extended Temperature device) TAmax 85a oC Minimum operating ambient temperature TAmin 0 o C Minimum operating ambient temperature (Extended Temperature device) TAmin -40 o C Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Electrical Characteristics 17.2 DC ELECTRICAL SPECIFICATIONS Table 17-5. DC ELECTRICAL SPECIFICATIONS Freescale Semiconductor, Inc... CHARACTERISTIC SYMBOL MIN MAX UNIT Operation voltage range VDD 3.0 3.6 V Input high voltage VIH 2 5.5 V Input low voltage VIL GND 0.
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Electrical Characteristics Freescale Semiconductor, Inc. 17.3 AC ELECTRICAL SPECIFICATIONS 17.3.1 Clock Input Timing Specifications Table 17-6. Clock Input Timing Specifications 40 MHz Freescale Semiconductor, Inc... NAME 54 MHz CHARACTERISTIC UNIT MIN MAX MIN MAX Frequency of Operation1 0 40.00 0 54.00 MHz C1 CLK cycle time 25 — 18.5 — ns C22 CLK fall time(from Vh =2.4VtoVl =0.5V) — 2 — 2 ns C32 CLK rise time (from Vl =0.5VtoVh =2.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.3 Processor Bus Input Timing Specifications Table 17-7. Processor Bus Input Timing Specifications 40 MHz NAME UNIT Freescale Semiconductor, Inc... MIN B1a B1b B1c B1d B1e B1f B1g B1h B1i B1j B2a B2b B2c B3a B3b B4a B4b B5 B6 54 MHz CHARACTERISTIC CONTROL INPUTS 5 TS Valid to CLK (Setup) TA, Valid to CLK (Setup) 5 1.5 ATA Valid to CLK (Setup) TEA Valid to CLK (Setup) 4.5 BG Valid to CLK (Setup) 5.5 1.
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Electrical Characteristics Freescale Semiconductor, Inc. 17.3.4 Input Timing Waveform Diagram * The same timings are valid for negative edge inputs 1.5V CLK TSETUP THOLD INPUT SETUP AND HOLD INVALID 1.5V VALID 1.5V INVALID trise = 1.5ns Freescale Semiconductor, Inc... INPUT RISE TIME Vh = VIH Vl = VIL tfall = 1.5ns INPUT FALL TIME Vh = VIH Vl = VIL Figure 17-2. Input Timing Waveform Requirements 17-6 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.5 Processor Bus Output Timing Specifications Table 17-8. Processor Bus Output Timing Specifications 40 MHz NAME UNIT Freescale Semiconductor, Inc...
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Electrical Characteristics Freescale Semiconductor, Inc. 17.3.6 Output Timing Waveform Diagram CLK (POSITIVE) 1.5V THOLD OUTPUT HOLD INVALID VALID 1.5V TVALID Freescale Semiconductor, Inc... OUTPUT VALID CLK (NEGATIVE) INVALID 1.5V VALID 1.5V THOLD OUTPUT INVALID VALID 1.5V TVALID OUTPUT INVALID 1.5V VALID Figure 17-3. Output Timing Waveform 17-8 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.7 Processor Bus Timing Diagrams CLK B1g RSTI B1f Freescale Semiconductor, Inc... IPL[2:0]/IRQ[7,4,1] B2c MODE SELECTS ARE REGISTERED ON THE PREVIOUS FALLING CLK EDGE BEFORE THE CYCLE IN WHICH RSTI IS RECOGNIZED AS BEING NEGATED. Figure 17-4. Reset Configuration Timing MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Electrical Characteristics Freescale Semiconductor, Inc. CLK B10 ADDRESS & ATTRIBUTES B11 B7a TS Freescale Semiconductor, Inc... B8a B10 B10 ATM B11 B11 B5 DATA IN (READ) B6 B13 B15 DATA OUT (WRITE) B14 B10 WE[3:0] B11 B1b TA B2a B1c ATA B2b B1d TEA B2a NOTE: ADDRESS AND ATTRIBUTES REFER TO THE FOLLOWING SIGNALS: A[27:0], SIZ[1:0], R/W, TT[1:0], ATM, AND CS[7:0]. Figure 17-5. Read and Write Timing 17-10 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Electrical Characteristics CLK B12 B10 ADDRESS & ATTRIBUTES B11 B8a B7a TS Freescale Semiconductor, Inc... B9 B8a B7f BR B8a B7f BD B8a B15 DATA OUT (WRITE) B14 B1e B1e BG B2a B2a NOTE: ADDRESS AND ATTRIBUTES REFER TO THE FOLLOWING SIGNALS: A[27:0], SIZ[1:0], R/W, TT[1:0], ATM, CS[7:0] AND WE[3:0]. Figure 17-6. Bus Arbitration Timing MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Electrical Characteristics Freescale Semiconductor, Inc. CLK B10 B10 ADDRESS B11 B11 B7a B7a TS B8a B7e DRAMW B8a Freescale Semiconductor, Inc... B7c RAS[1:0] B8a B7d B8b B8b CAS[3:0] B8b B8b B5 DATA IN (READ) B6 B13 DATA OUT B13 (WRITE) B15 B14 B14 Figure 17-7. DRAM Signal Timing CLK B7e DRAMW B8a B7d CAS[3:0] B8b B7c RAS[1:0] B8a Figure 17-8. DRAM Refresh Cycle Timing 17-12 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Electrical Characteristics CLK ALT. MASTER B3 B3 ADDRESS, B4 B1a SIZ[1:0], R/W IN ALT. MASTER TS IN B4 B1a B2a B2a B10 B10 ADDRESS Freescale Semiconductor, Inc... B11 B12 B7e DRAMW B7c RAS[1:0] B8a B7d B8b CAS[3:0] B8b B7b B7b TA B7b B8a B9 Figure 17-9. DRAM Control By External Master Timing MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Electrical Characteristics Freescale Semiconductor, Inc. CLK B1h B1h DSCLK B2a B2a B1g RSTI Freescale Semiconductor, Inc... B2b B1j BKPT B2b B1i DSI B2a B1f IPL[2:0]/IRQ[7,4,1] B2b B7g RSTO B8a B7h PST[3:0], DSO, DDATA[3:0] B8a NOTE: SIGNALS ABOVE ARE SHOWN IN RELATION TO THE CLOCK. NO RELATIONSHIP BETWEEN SIGNALS IS IMPLIED OR INTENDED. ALL OUTPUTS B16 B17 HIZ Figure 17-10. Miscellaneous Signal Timing 17-14 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.8 Timer Module AC Timing Specifications Table 17-9. Timer Module AC Timing Specifications 40 MHz NAME Freescale Semiconductor, Inc... T1 T2 T3 T4 T5 T6 T7 54 MHz CHARACTERISTIC UNIT TIN[1:0] cycle time TIN[1:0] Valid to CLK (Setup) CLK to TIN[1:0] Invalid (Hold) CLK to TOUT[1:0] Valid CLK to TOUT[1:0] Invalid (Output Hold) TIN[1:0] pulse width TOUT[1:0] pulse width MIN MAX MIN MAX 3 4 4.5 3 3 1 1 — — — 22 — — — 3 2.5 4.
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Electrical Characteristics Freescale Semiconductor, Inc. 17.3.10 UART Module AC Timing Specifications Table 17-10. UART Module AC Timing Specifications Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.12 M-BUS Module AC Timing Specifications 17.3.12.1 INPUT TIMING SPECIFICATIONS BETWEEN SCL AND SDA. Table 17-11. INPUT Timing Specifications Between SCL and SDA 40 MHz Freescale Semiconductor, Inc... NAME 54 MHz CHARACTERISTIC UNIT MIN MAX MIN MAX M11 Start condition hold time 2 — 2 — CLKs M21 Clock low period 8 — 8 — CLKs M3 SCL/SDA rise time (from Vl =0.5V to Vh =2.
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Electrical Characteristics Freescale Semiconductor, Inc. 17.3.12.2 OUTPUT TIMING SPECIFICATIONS BETWEEN SCL AND SDA. Table 17-12. Output Timing Specifications Between SCL and SDA 40 MHz Freescale Semiconductor, Inc... NAME 54 MHz CHARACTERISTIC UNIT MIN MAX MIN MAX M11,2 Start condition hold time 6 — 6 — CLKs M21,2 Clock low period 10 — 10 — CLKs M33 SCL/SDA rise time (from Vl =0.5V to Vh =2.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.13 M-Bus Module Timing Diagram M2 M6 M5 Vh Vl SCL M1 M4 M7 M8 M3 M9 SDA Freescale Semiconductor, Inc... CLK M10 SCL, SDA IN M11 M12 SCL, SDA OUT SCL, SDA OUT M13 Figure 17-13. M-Bus Timing MOTOROLA MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
PAGE 476
Electrical Characteristics Freescale Semiconductor, Inc. 17.3.14 General-Purpose I/O Port AC Timing Specifications Table 17-14. General-Purpose I/O Port AC Timing Specifications 40 MHz NAME P1 P2 P3 P4 54 MHz CHARACTERISTIC UNIT PP[7:0]input setup time to CLK (rising) PP[7:0] input hold time from CLK (rising) CLK to PP[7:0] Output Valid CLK to PP[7:0] Output Invalid (Output Hold) MIN MAX MIN MAX 3 4.5 3 3 — — 19.5 — 2 4.5 3 3 — — 17 — ns ns ns ns Freescale Semiconductor, Inc... 17.3.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.16 DMA Controller AC Timing Specifications Table 17-15. DMA Controller AC Timing 40 MHz NAME D1 D2 54 MHz CHARACTERISTIC UNIT DREQ Valid to CLK (Setup) CLK to DREQ Invalid (Hold) MIN MAX MIN MAX 4 4.5 — — 2.5 4.5 — — ns ns Freescale Semiconductor, Inc... 17.3.17 DMA Controller Timing Diagram CLK D1 DREQ IN D2 Figure 17-15. DMA Timing 17.3.18 IEEE 1149.1 (JTAG) AC Timing Specifications Table 17-16. IEEE 1149.
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Freescale Semiconductor, Inc. Electrical Characteristics 17.3.19 IEEE 1149.1 (JTAG) Timing Diagram J3a J1 Vh J3b Vl TCK J2a J2b J4 TDI, TMS J5 J6 BOUNDARY SCAN DATA J7 INPUTS Freescale Semiconductor, Inc... J8 TRST J9 J10 J11 J12 TDO BOUNDARY SCAN DATA OUTPUTS Figure 17-16. IEEE 1149.1 (JTAG) Timing 17-22 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. SECTION 18 MECHANICAL DATA S S D D L C A-B S –A–, –B–, –D– B B M V 0.20 (0.008) H A-B M B L 0.20 (0.008) A-B –B– –A– 0.20 (0.008) Freescale Semiconductor, Inc... S Y P DETAIL A G DETAIL A Z –D– A 0.20 (0.008) M H A-B S D BASE METAL S 0.20 (0.008) A-B 0.20 (0.008) M ÇÇÇÇÇ ÉÉÉ ÇÇÇÇÇ ÉÉÉ ÇÇÇÇÇ N S C A-B S D S DETAIL C J F D –H– 0.13 (0.
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Mechanical Data Freescale Semiconductor, Inc. 18.
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Freescale Semiconductor, Inc. Mechanical Data Table 18-1. MCF5206e Package/Frequency Availability Package Frequency Temperature Part Number Plastic Quad Flat Pack 160 lead 40, and 54 MHz 0 to 70 C MCF5206E Plastic Quad Flat Pack 160 lead 40 MHz -40 to +85 C 18.2 DOCUMENTATION All MCF5206e information is available on the WWW at http://sps.motorola.com/coldfire. Hard copy information is available from Motorola literature distribution centers. Freescale Semiconductor, Inc... Table 18-2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Mechanical Data 18-4 MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. A B APPENDIX A MCF5206E MEMORY MAP SUMMARY C This section is a summary chart of the entire memory map for the MCF5206e. D Freescale Semiconductor, Inc... Table A-1.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Appendix A Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Appendix A A B C D Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. A APPENDIX B PORTING FROM M68000 FAMILY DEVICES C This section is an overview of the issues encountered when porting embedded development tools to ColdFire® devices when starting with the M68000 Family devices. D Freescale Semiconductor, Inc... B.1 C COMPILERS AND HOST SOFTWARE For the purpose of this discussion, it is assumed that an embedded software development tool chain consists of a “host” portion and a “target” portion.
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Appendix B A B C D Freescale Semiconductor, Inc. To generate a ColdFire device executable of the target debugger, you should use a compliant port of the same C compiler originally used to create the M68000 Family debugger target. This procedure prevents differences in calling convention and parameter passing from C to handwritten assembly. Another advantage to this approach is that special C flags are retained. Many C compilers have special extensions as well.
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Freescale Semiconductor, Inc. Appendix B System calls are often implemented by using the TRAP instruction. For trap exceptions, parameter passing is performed through data and address registers—rarely, if ever, directly through the stack. In addition, a system call typically does not need to know the stacked SR or PC information. Freescale Semiconductor, Inc... Breakpoints are usually implemented with the TRAP instruction or an illegal instruction such as an $A-line exception.
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Appendix B Freescale Semiconductor, Inc. A B C D Freescale Semiconductor, Inc... E F G H I J K L M N O P Appendix B-iv MCF5206e USER’S MANUAL For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. INDEX Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Index Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Index Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. M-Bus Interrupt 8-5, 13-8, 13-10 M-Bus module 1-16 M-Bus Serial Clock 2-16 M-Bus Serial Data 2-16 Memory-to-Memory Transfer 7-5 MFDR 13-6 Misaligned Operands 6-48 Module Base Address Register 8-1 Motorola Test Mode 2-20 MOVEM 6-19 MTMOD 2-17, 2-19 multidrop mode 12-14, 12-18, 12-27 Multiplexed Address 11-52 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Index Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Introduction 1 Signal Description 2 ColdFire Core 3 Instruction Cache 4 SRAM 5 Bus Operation 6 DMA Controller Module 7 System Integration Module (SIM) 8 Chip Select Module 9 Parallel Port (General-Purpose I/O) 10 DRAM Controller 11 UART Modules 12 MBus Module 13 Timer Module 14 Debug Support 15 IEEE 1149.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1 Introduction 2 Signal Description 3 ColdFire Core 4 Instruction Cache 5 SRAM 6 Bus Operation 7 DMA Controller Module 8 System Integration Module (SIM) 9 Chip Select Module 10 Parallel Port (General-Purpose I/O) 11 DRAM Controller 12 UART Modules 13 M-Bus Module 14 Timer Module 15 Debug Support 16 IEEE 1149.