Datasheet

Instruction Cache

4-8 MCF5206e USER’S MANUAL MOTOROLA

DCM - Default Cache Mode

This bit defines the default cache mode: 0 is cacheable, 1 is noncacheable. For more

information on the selection of the effective memory attributes, see Section 4.3.2

Memory Reference Attributes.

0 = Deafault cacheable

1 = Default noncacheable

DBWE - Default Buffered Write Enable

This bit defines the default value for enabling buffered writes. If DBWE = 0, the termination

of an operand write cycle on the processor's local bus is delayed until the external bus

cycle is completed. If DBWE = 1, the write cycle on the local bus is terminated immediately

and the operation buffered in the bus controller. In this mode, operand write cycles are

effectively decoupled between the processor's local bus and the external bus.

Generally, enabled buffered writes provide higher system performance but recovery from

access errors can be more difficult. For the ColdFire CPU, reporting access errors on

operand writes is always imprecise and enabling buffered writes simply further decouples

the write instruction from the signaling of the fault

0 = Disable buffered writes

1 = Enable buffered writes

DWP - Default Write Protection

0 = Read and write accesses permitted

1 = Only read accesses permitted

CLNF[1:0] - Cache Line Fill

These bits control the size of the memory request the cache issues to the bus controller

for different initial line access offsets.

4.4.2.2 ACCESS CONTROL REGISTERS (ACR0, ACR1). The ACRs provide a

definition of memory reference attributes for two memory regions (one per ACR). This set

of effective attributes is defined for every memory reference using the ACRs or the set of

default attributes contained in the CACR. The ACRs are examined for every memory

reference that is NOT mapped to the SRAM module.

Table 4-4. External Fetch Size Based on Miss Address and CLNF

CLNF[1:0]

LONGWORD ADDRESS BITS

00 01 10 11

00 Line Line Line Longword

01 Line Line Longword Longword

10 Line Line Line Line

11 Line Line Line Line

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