Datasheet

Instruction Cache
MOTOROLA MCF5206e USER’S MANUAL 4-9
The ACRs are 32-bit write-only supervisor control registers. They are accessed in the
CPU address space via the MOVEC instruction with an Rc encoding of $004 and $005.
The ACRs can be read when in background debug mode (BDM). At system reset, the
registers are cleared.
AB[31:24] - Address Base [31:24]
This 8-bit field is compared to address bits [31:24] from the processor's local bus under
control of the ACR address mask. If the address matches, the attributes for the memory
reference are sourced from the given ACR.
AM[31:24] - Address Mask [31:24]
This 8-bit field can mask any bit of the AB field comparison. If a bit in the AM field is set,
then the corresponding bit of the address field comparison is ignored.
EN - Enable
The EN bit defines the ACR enable. Hardware reset clears this bit, disabling the ACR.
0 = ACR disabled
1 = ACR enabled
SM[1:0] - Supervisor mode
This two-bit field allows the given ACR to be applied to references based on operating
privilege mode of the ColdFire processor. The field uses the ACR for user references only,
supervisor references only, or all accesses.
00 = Match if user mode
01 = Match if supervisor mode
1x = Match always - ignore user/supervisor mode
AB31 AB30 AB29 AB28 AB27 AB26 AB25 AB24 AM31 AM30 AM29 AM28 AM27 AM26 AM25 AM24
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
RESET:
ENSM1SM0------CMBUFW--WP--
1514131211109876543210
0000000000000000
RESET:
Access Control Registers (ACR0, ACR1)
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