Datasheet

MOTOROLA MCF5206e USER’S MANUAL 5-1
SECTION 5
SRAM
5.1 SRAM FEATURES
• 8 KByte SRAM, organized as 2K x 32 Bits
• Single-Cycle Access
• Physically Located on ColdFire
®
core's High-Speed Local Bus
• Byte, Word, Longword Address Capabilities
• Memory Mapping Defined by the Customer
5.2 SRAM OPERATION
The SRAM module provides a general-purpose memory block that the ColdFire core can
access in a single cycle. You can specify the location of the memory block to any 0-modulo-
8K address within the four gigabyte address space. The memory is ideal for storing critical
code or data structures or for use as the system stack. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can service core-initiated
accesses or memory-referencing commands from the Debug module.
Depending on configuration information, instruction fetches can be sent to both the
instruction cache and the SRAM block simultaneously. If the instruction fetch address is
mapped into the region defined by the SRAM, the SRAM provides the data back to the
processor, and the I-Cache data is discarded. Accesses from the SRAM and cache
interaction are not cached.
5.3 PROGRAMMING MODEL
5.3.1 SRAM Register Memory Map
Table 5-1 below shows the memory map of the SRAM register.
The following lists several keynotes regarding the programming model table:
• The SRAM Base Address Register can only be accessed in supervisor mode using the
MOVEC instruction with an Rc value of $C04.
• Addresses not assigned to the register and undefined register bits are reserved for
future expansion. Write accesses to these reserved address spaces and reserved
register bits have no effect; read accesses will return zeros.
• The reset value column indicates the register initial value at reset. Certain registers can
be uninitialized at reset, i.e., they may contain random values after reset.
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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