Datasheet

SRAM
5-2 MCF5206e USER’S MANUAL MOTOROLA
• The access column indicates if the corresponding register allows both read/write
functionality (R/W), read-only functionality (R), or write-only functionality (W). If a
read access to a write-only register is attempted, zeros will be returned. If a write
access to a read-only register is attempted the access will be ignored and no write
will occur.
5.3.2 SRAM Register
5.3.2.1 SRAM BASE ADDRESS REGISTER (RAMBAR). The RAMBAR determines
the base address location of the internal SRAM module, as well as the definition of the
types of accesses that are allowed for it.
The RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the CPU
address space via the MOVEC instruction with an Rc encoding of $C04. The RAMBAR
can be read when in Background Debug mode (BDM). At system reset, the V bit is cleared
and the remainder bits of the RAMBAR are uninitialized. To access the SRAM module,
RAMBAR should be written with the appropriate base address after system reset.
BA31-BA13 - Base Address
This field defines the base address location of the SRAM module. By programming this
field, you can locate the SRAM anywhere within the four gigabyte ColdFire core address
space.
WP - Write Protect
This field allows only read accesses to the SRAM. When this bit is set, any attempted write
access will generate an access error exception in the MCF5206e.
0 = Allow read and write accesses to the SRAM module
1 = Allow only read accesses to the SRAM module
Table 5-1. Memory Map of SIM Registers
ADDRESS NAME WIDTH DESCRIPTION RESET VALUE ACCESS
MOVEC with $C04 RAMBAR 32 SRAM Base Address Register
uninitialized
(except V=0)
W
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
----------------
RESET:
BA15 BA14 BA13 - - - -- WP - - C/I SC SD UC UD V
1514131211109876543210
--------00-----0
RESET:
SRAM Base Address Register(RAMBAR)
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