Datasheet

SRAM
MOTOROLA MCF5206e USER’S MANUAL 5-3
C/I, SC, SD, UC, UD - Address Space Masks
This field allows specific address spaces to be enabled or disabled, placing the internal
modules in a specific address space. If an address space is disabled, an access to the
register location in that address space becomes an external bus access, and the module
resource is not accessed. The address space mask bits are:
C/I = CPU Space/Interrupt Acknowledge Cycle mask
SC = Supervisor Code address space mask
SD = Supervisor Data address space mask
UC = User Code address space mask
UD = User Data address space mask
For each address space bit:
0= An access to the internal module can occur for this address space.
1= Disable this address space from the internal module selection. If this address
space is used, no accesses occur to the internal peripheral, instead an external
bus cycle will be generated.
V - Valid
This bit indicates when the contents of the RAMBAR are valid. The base address value is
not used, and the SRAM module is not accessible until the V bit is set. An external bus
cycle is generated if the base address field matches the internal core address, and the V
bit is clear.
0 = Contents of RAMBAR are not valid.
1 = Contents of RAMBAR are valid.
The mapping of a given access into the SRAM uses the following algorithm to determine
if the access “hits” in the memory:
if (RAMBAR[0] = 1)
if (requested address[31:9] = RAMBAR[31:9])
if (address space mask of the requested type = 0)
Access is mapped to the SRAM module
if (access = read)
Read the SRAM and return the data
if (access = write)
if (RAMBAR[8] = 0)
Write the data into the SRAM
else Signal a write-protect access error
5.3.3 SRAM Initialization
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of
the RAMBAR is cleared, disabling the module. If the SRAM needs to be initialized with
instructions or data, you should perform the following steps:
1. Load the RAMBAR mapping the SRAM module to the desired location within the
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