Datasheet

SRAM

5-4 MCF5206e USER’S MANUAL MOTOROLA

address space.

2. Read the source data and write it to the SRAM. There are various instructions to

support this function, including memory-to-memory move instructions, or the

MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst

fetches on 0-modulo-16 addresses, so this opcode generally provides maximum

performance.

3. After the data has been loaded into the SRAM, it may be appropriate to load a

revised value into the RAMBAR with a new set of attributes. These attributes consist

of the write-protect and address space mask fields.

The ColdFire processor or an external emulator using the Debug module can perform

these initialization functions.

5.3.4 Power Management

As noted previously, depending on the configuration defined by the RAMBAR, instruction

fetch accesses can be sent to the SRAM module and the I-Cache simultaneously. If the

access is mapped to the SRAM module, it sources the read data, discarding the I-Cache

access. If the SRAM is used only for data operands, setting the SC and UC mask bits in

the RAMBAR to 1 will lower power dissipation. This will disable the SRAM during all

instruction fetches. Additionally, if the SRAM contains only instructions, setting the SD and

UD mask bits in the RAMBAR to 1 masking operand accesses will reduce power

dissipation.

Consider the examples on Table 5-2 of typical RAMBAR settings:

Table 5-2. Examples of Typical RAMBAR Settings

DATA CONTAINED IN SRAM RAMBAR[7:0]

Code only $2B

Data only $35

Both Code and Data $21

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