Datasheet

MOTOROLA MCF5206e USER’S MANUAL 6-1

SECTION 6

BUS OPERATION

The MCF5206e bus interface supports synchronous data transfers that can be terminated

synchronously or asynchronously and also can be burst or burst-inhibited between the

MCF5206e and other devices in the system. This section describes the function of the bus,

the signals that control the bus, and the bus cycles provided for data-transfer operations.

Operation of the bus is defined for transfers initiated by the MCF5206e as a bus master and

for transfers initiated by an external bus master. When the DMA Controller has mastership,

it is explicitly stated. The section includes descriptions of the error conditions, bus

arbitration, and the reset operation.

6.1 FEATURES

The following list summarizes the key bus operation features:

• As many as 28 bits of address and 32 bits of data

• Accesses 8 bit, 16 bit, and 32 bit port sizes

• Generates byte, word, longword, and line size transfers

• Bus arbitration for external masters

• Burst and burst-inhibited transfer support

• Internal termination generation

• Termination generation for external masters

6.2 BUS AND CONTROL SIGNALS

6.2.1 Address Bus (A[27:0])

These three-state bidirectional signals provide the location of a bus transfer (except for

interrupt-acknowledge transfers) when the MCF5206e is the bus master. When an external

bus master controls the bus, the address signals are examined when transfer start (TS

) is

asserted to determine if the MCF5206e should assert chip selects, DRAM control, and/or

transfer terminal signals. During an interrupt-acknowledge access, address lines A[27:5] are

driven high, A[1:0] are driven low, and A[4:2] indicate the interrupt level being

acknowledged.

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Freescale Semiconductor, Inc.

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