Datasheet

Bus Operation
6-2 MCF5206e USER’S MANUAL MOTOROLA
NOTE
The ColdFire
®
core outputs 32 bits of address to the internal
bus controller. Of these 32 bits, only A[27:0] are output to pins
on the MCF5206e. The output of A[27:24] depends on the
setting of PAR[3:0] in the Pin Assignment Register (PAR) in
the SIM. Refer to 6.3.2.10 Pin Assignment Register on how
to program the Pin Assignment Register (PAR).
6.2.2 Data Bus (D[31:0])
These three-state bidirectional signals provide the general-purpose data path between
the MCF5206e and all other devices. The data bus can transfer 8, 16, 32, or 128 bits of
data per bus transfer. A write cycle drives all 32 bits of the data bus regardless of the port
width and operand size.
6.2.3 Transfer Start (TS)
The MCF5206e asserts this three-state bidirectional signal for one clock period to indicate
the start of each bus cycle. During external master accesses, the MCF5206e monitors
transfer start (TS) to detect the start of each external master bus cycle to determine if chip
select, DRAM, and/or transfer termination signals should be asserted.
6.2.4 Read/Write (R/W)
This three-state bidirectional signal defines the data transfer direction for the current bus
cycle. A high (logic one) level indicates a read cycle; a low (logic zero) level indicates a
write cycle. When an external bus master is controlling the bus, the MCF5206e monitors
this signal to determine if chip selects or DRAM control signals should be asserted.
6.2.5 Size (SIZ[1:0])
These three-state bidirectional signals indicate the data size for the bus cycle. When an
external bus master is controlling the bus, the MCF5206e monitors these signals to
determine the data size for asserting the appropriate memory control signals. Table 6-1
shows the definitions of the SIZx encoding.
Table 6-1. SIZx Encoding
SIZ1 SIZ0 TRANSFER SIZE
0 0 Longword (4 Bytes)
01 Byte
1 0 Word (2 Bytes)
1 1 Line (16 Bytes)
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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