Datasheet

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MOTOROLA MCF5206e USER’S MANUAL ix
2.13.2 Parallel Port (General-Purpose I/O) (PP[3:0]/DDATA[3:0]) ......2-16
2.14 Debug Support Signals ......................................................................2-16
2.14.1 Processor Status (PP[7:4]/PST[3:0]) ........................................2-16
2.14.2 Debug Data (PP[3:0]/DDATA[3:0]) ...........................................2-17
2.14.3 Development Serial Clock (TRST/DSCLK) ..............................2-17
2.14.4 Break Point (TMS/BKPT) .........................................................2-18
2.14.5 Development Serial Input (TDI/DSI) .........................................2-18
2.14.6 Development Serial Output (TDO/DSO) ..................................2-18
2.15 JTAG Signals .....................................................................................2-18
2.15.1 Test Clock (TCK) ......................................................................2-18
2.15.2 Test Reset (TRST/DSCLK) ......................................................2-18
2.15.3 Test Mode Select (TMS/BKPT) ................................................2-19
2.15.4 Test Data Input (TDI/DSI) .........................................................2-19
2.15.5 Test Data Output (TDO/DSO) ..................................................2-19
2.16 Test Signals ........................................................................................2-20
2.16.1 Motorola Test Mode (MTMOD) ................................................2-20
2.16.2 High Impedance (HIZ) ..............................................................2-20
2.17 Signal Summary .................................................................................2-20
Section 3
ColdFire Core
3.1 Processor Pipelines ..............................................................................3-1
3.2 Processor Register Description ............................................................3-2
3.2.1 User Programming Model ..........................................................3-2
3.2.1.1 Data Registers (D0–D7) .................................................3-2
3.2.1.2 Address Registers (A0–A6) ............................................3-2
3.2.1.3 Stack Pointer (A7) ...........................................................3-2
3.2.1.4 Program Counter ............................................................3-2
3.2.1.5 Condition Code Register .................................................3-3
3.2.2 MAC Unit User Programming Model ..........................................3-4
3.2.3 Hardware Divide Module ............................................................3-4
3.2.4 Supervisor Programming Model .................................................3-4
3.2.4.1 Status Register ...............................................................3-4
3.2.4.2 Vector Base Register (VBR) ...........................................3-5
3.3 Exception Processing Overview ...........................................................3-5
3.4 Exception Stack Frame Definition ........................................................3-7
3.5 Processor Exceptions ...........................................................................3-8
3.5.1 Access Error Exception ..............................................................3-8
3.5.2 Address Error Exception ............................................................3-9
3.5.3 Illegal Instruction Exception ........................................................3-9
3.5.4 Privilege Violation .......................................................................3-9
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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