Datasheet

Bus Operation
6-4 MCF5206e USER’S MANUAL MOTOROLA
6.2.8 Asynchronous Transfer Acknowledge (ATA)
This active-low asynchronous input signal indicates the successful completion of a
requested data transfer operation. Asynchronous transfer acknowledge (ATA) is an input
signal from the referenced slave device indicating completion of the transfer. ATA is
synchronized internal to the MCF5206e.
NOTE
The internal synchronized version of ATA is referred to as
“internal asynchronous transfer acknowledge.’’ During a read
cycle, data is latched on the rising edge of CLK when the
internal asynchronous transfer acknowledge is asserted.
Consequently, data must remain valid for at least one and a
half CLK cycles after the assertion of ATA. Similarly, during a
write cycle, data is driven until the falling edge of CLK when
the internal asynchronous transfer acknowledge is asserted.
ATA must be driven for one and half full clocks to ensure that the MCF5206e properly
synchronizes the signal.
NOTE
For the MCF5206e to accept the transfer as successful with
an ATA, transfer error acknowledge TEA must be negated
until the internal asynchronous transfer acknowledge is
asserted or the transfer is completed with a bus error.
Asynchronous transfer acknowledge (ATA) is not used for termination during DRAM
accesses.
6.2.9 Transfer Acknowledge (TA)
This three-state bidirectional active-low synchronous signal indicates the successful
completion of a requested data transfer operation. During MCF5206e-initiated transfers,
transfer acknowledge (TA
) is an input signal from the referenced slave device indicating
completion of the transfer.
NOTE
For the MCF5206e to accept the transfer as successful with a
transfer acknowledge, TEA
must be negated throughout the
transfer.
TA
is not used for termination during MCF5206e-initiated DRAM accesses.
When an external master is controlling the bus, the MCF5206e can drive TA
to indicate
the completion of the requested data transfer. If the external master-requested transfer is
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