Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-5
to a chip select or default memory, the assertion of TA is controlled by the number of wait
states and the setting of the external master automatic acknowledge (EMAA) bit in the
Chip Select Control Registers (CSCRs) or the Default Memory Control Register (DMCR).
If the external master-requested transfer is a DRAM access, the MCF5206e drives TA as
an output and is asserted at the completion of the transfer.
6.2.10 Transfer Error Acknowledge (TEA)
The external slave asserts this active-low input signal to indicate an error condition for the
current transfer. The assertion of TEA immediately aborts the bus cycle. The assertion
of TEA has precedence over the assertion of asynchronous transfer acknowledge (ATA)
and transfer acknowledge (TA).
NOTE
TEA can be asserted up to one clock after the assertion of
asynchronous transfer acknowledge (ATA) and still be
recognized.
TEA has no affect during DRAM accesses.
6.3 BUS EXCEPTIONS
6.3.1 Double Bus Fault
If the MCF5206e experiences a double bus fault, it enters the halted state. To exit the halt
state, reset the MCF5206e.
6.4 BUS CHARACTERISTICS
The MCF5206e uses the address bus (A[27:0]) to specify the location for a data transfer
and the data bus (D[31:0]) to transfer the data. Control and attribute signals indicate the
beginning and type of a bus cycle as well as the address space, direction, and size of the
transfer. The selected device or the number of wait states programmed in the memory
control register (the Chip Select Control Register (CSCR), the DRAM Controller Control
Registers (DCCR, including the DRAM Controller Timing Register (DCTR)), or the Default
Memory Control Register (DMCR)) control the length of the cycle.
The MCF5206e clock is distributed internally to provide logic timing. All bus signals are
synchronous with the rising edge of CLK with the exception of row address strobes
(RAS[1:0]) and column address strobes (CAS[3:0]), which can be asserted and negated
synchronous with the falling edge of CLK.
Inputs to the MCF5206e (other than the interrupt priority level signals (IPLx), reset in
(RSTI) and ATA signals) are synchronously sampled and must be stable during the
sample window defined by t
si
and t
hi
(as shown in Figure 6-1) to guarantee proper
operation. The asynchronous IPLx
, RSTI and ATA signals are internally synchronized to
resolve the input to a valid level before being used.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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