Datasheet

Bus Operation
6-6 MCF5206e USER’S MANUAL MOTOROLA
Outputs to the MCF5206e begin to transition on the rising CLK edges, with the exception
of RAS[1:0] and CAS[3:0], which begin to transition on the falling CLK edges. Specifically,
RAS[1:0] is asserted and negated synchronous with the falling edge of CLK, while
CAS[3:0] is asserted synchronous with the falling edge of CLK and can be negated
synchronous with either the falling edge or the rising edge of CLK.
During external master accesses where the MCF5206e drives TA as an output, TA is
always driven negated for one clock cycle before being placed in a high-impedence state.
Figure 6-1. Signal Relationships to CLK
6.5 DATA TRANSFER MECHANISM
The MCF5206e supports byte, word, and longword operands and allows accesses to 8-,
16-, and 32-bit data ports. With the MCF5206e, you can select the port size of the specific
memory, enable internal generation of transfer termination, and set the number of wait
states for the external slave being accessed by programming the Chip Select Control
Registers (CSCRs), the DRAM Controller Control Registers (DCCRs), and the Default
Memory Control Register (DMCR). For more information on programming these registers,
refer to the SIM, Chip Select, and DRAM Controller sections.
NOTE
The MCF5206e compares the address for the current bus
transfer with the address and mask bits in the Chip Select
CLK
OUTPUT
SIGNALS
INPUTS
T
VO
T
HO
T
VO
T
HO
T
SI
T
HI
T
VO
= PROPAGATION DELAY OF SIGNAL RELATIVE TO CLK EDGE
T
HO
= OUTPUT HOLD TIME RELATIVE TO CLK EDGE
T
SI
= REQUIRED INPUT SETUP TIME RELATIVE TO CLK EDGE
T
HI
= REQUIRED INPUT HOLD TIME RELATIVE TO CLK EDGE
NEGATIVE EDGE
CONTROL SIGNALS
OUTPUT
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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