Datasheet

Bus Operation
6-12 MCF5206e USER’S MANUAL MOTOROLA
Figure 6-5 shows a longword supervisor code read from a 32-bit port.
Figure 6-5. Longword-Read Transfer From a 32-Bit Port (No Wait States)
Clock 1 (C1)
The read cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type. Access type and mode (ATM) identifies the transfer as reading code.
The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0])
are driven low to indicate a longword transfer. The MCF5206e asserts transfer start (TS)
to indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates transfer start (TS), drives access type and mode
(ATM) high to identify the transfer as supervisor. The selected device(s) places the
addressed data onto D[31:0] and asserts the transfer acknowledge (TA). At the end of C2,
the MCF5206e samples the level of TA and if TA is asserted, latches the current value of
D[31:0]. If TA is asserted, the transfer of the longword is complete and the transfer
terminates. If TA is negated, the MCF5206e continues to sample TA and inserts wait
states instead of terminating the transfer. The MCF5206e continues to sample TA on
successive rising edges of CLK until it is asserted. If the bus monitor timer is enabled and
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$0
$0
$ADDR
ATA
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...