Datasheet

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
x MCF5206e USER’S MANUAL MOTOROLA
3.5.5 Trace Exception .........................................................................3-9
3.5.6 Debug Interrupt ........................................................................3-10
3.5.7 RTE and Format Error Exceptions ...........................................3-10
3.5.8 TRAP Instruction Exceptions ...................................................3-10
3.5.9 Interrupt Exception ...................................................................3-10
3.5.10 Fault-on-Fault Halt ...................................................................3-11
3.5.11 Reset Exception .......................................................................3-11
3.6 Instruction Execution Timing ..............................................................3-11
3.6.1 Timing Assumptions .................................................................3-11
3.6.2 MOVE Instruction Execution Times .........................................3-12
Section 4
Instruction Cache
4.1 Features of Instruction Cache ..............................................................4-1
4.2 Instruction Cache Physical Organization .............................................4-1
4.3 Instruction Cache Operation ................................................................4-2
4.3.1 Interaction With Other Modules ..................................................4-3
4.3.2 Memory Reference Attributes ....................................................4-3
4.3.3 Cache Coherency and Invalidation ............................................4-3
4.3.4 Reset ..........................................................................................4-4
4.3.5 Cache Miss Fetch Algorithm/Line Fills .......................................4-4
4.4 Instruction Cache Programming Model ................................................4-5
4.4.1 Instruction Cache Registers Memory Map .................................4-5
4.4.2 Instruction Cache Register .........................................................4-6
4.4.2.1 Cache Control Register (CACR) .....................................4-6
4.4.2.2 Access Control Registers (ACR0, ACR1) .......................4-8
Section 5
SRAM
5.1 SRAM Features ....................................................................................5-1
5.2 SRAM Operation ..................................................................................5-1
5.3 Programming Model .............................................................................5-1
5.3.1 SRAM Register Memory Map ....................................................5-1
5.3.2 SRAM Register ..........................................................................5-2
5.3.2.1 SRAM Base Address Register (RAMBAR) .....................5-2
5.3.3 SRAM Initialization .....................................................................5-3
5.3.4 Power Management ...................................................................5-4
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...