Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-15
Figure 6-7 shows a supervisor data word-write transfer to a 16-bit port.
Figure 6-7. Word-Write Transfer to a 16-Bit Port (No Wait States)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type. Access type and mode (ATM) identifies the transfer as writing data.
The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0])
are driven to $2 to indicate a word transfer. The MCF5206e asserts transfer start (TS) to
indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates transfer start (TS), drives ATM high to identify the
transfer as supervisor, and places the data on the data bus (D[31:0]). The selected
device(s) asserts the transfer acknowledge (TA) if it is ready to latch the data. At the end
of C2, the selected device latches the current value of D[31:16], and the MCF5206e
samples the level of TA
. If TA is asserted, the transfer of the word is complete and the
transfer terminates. If TA
is negated, the MCF5206e continues to output the data and
inserts wait states instead of terminating the transfer. The MCF5206e continues to sample
TA
on successive rising edges of CLK until it is asserted.
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$2
$0
ATA
$ADDR
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