Datasheet

Bus Operation
6-16 MCF5206e USER’S MANUAL MOTOROLA
6.5.2 Bursting Read Transfers: Word, Longword, and Line
If the burst-enable bit in the appropriate control register (Chip Select Control Register or
Default Memory Control Register) is set to 1or the transfer is to DRAM, and the operand
size is larger than the port size of the memory being accessed, the MCF5206e performs
word, longword, and line transfers in burst mode. When burst mode is selected, the size
of the transfer (indicated by SIZ[1:0]) reflects the size of the operand being read, not the
size of the port being accessed (i.e., a line transfer is indicated by SIZ[1:0] = $3 and a
longword transfer is indicated by SIZ[1:0] = $0, regardless of the size of the port or the
number of transfers required to access the entire set of data).
The MCF5206e supports burst-inhibited transfers for memory devices that cannot support
bursting. For this type of bus cycle, you should clear the burst-enable bit in the Chip Select
Control Registers (CSCRs) or Default Memory Control Register (DMCR).
NOTE
No burst-enable bit is provided for DRAM accesses. DRAM
transfers are always bursted if the operand size is larger than
the port size.
The MCF5206e uses line read transfers to access 16 Bytes to support cache line filling
and for a MOVEM instruction, when appropriate. A line read accesses a block of four
longwords, aligned to a longword memory boundary, by supplying a starting address that
points to one of the longwords and incrementing A3, A2, A1, and A0 of the supplied
address for each transfer. A longword read accesses a single longword aligned to a
longword boundary and increments A1 and A0 if the accessed port size is smaller than 32
bits. A word read accesses a single word of data, aligned to a word boundary and
increments A0 if the accessed port size is smaller than 16 bits.
Figure 6-8 is a flowchart for bursting read transfers to 8-, 16-, or 32-bit ports. Bus
operations are similar for each case and vary only with the size indicated, the portion of
the data bus used for the transfer, and the specific number of cycles needed for each
transfer. A bursted read transfer can be from two to sixteen transfers long. The flowchart
shown in Figure 6-8 is for a bursting transfer of four transfers long.
Fr
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Freescale Semiconductor, Inc.
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