Datasheet

Bus Operation
6-18 MCF5206e USER’S MANUAL MOTOROLA
Figure 6-9 shows a bursting user code word-read transfer from an 8-bit port.
Figure 6-9. Bursting Word-Read From an 8-Bit Port (No Wait States)
Clock 1 (C1)
The read cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type. Access transfer and mode (ATM) identifies the transfer as reading
code. The read/write (R/W) signal is driven high for a read cycle, and the size signals
(SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206e asserts transfer
start (TS
) to indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates TS
, drives ATM low to identify the transfer as user.
The selected device(s) places the first byte of the addressed data on to D[31:24] and
asserts the transfer acknowledge (TA). At the end of C2, the MCF5206e samples the level
of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the
transfer of the first byte of the word read is complete. If TA
is negated, the MCF5206e
continues to sample TA
and inserts wait states instead of terminating the transfer. The
MCF5206e continues to sample TA on successive rising edges of CLK until it is asserted.
TS
A[27:1]
R/W
CLK
TT[1:0]
AT M
TA
D[31:24]
TEA
SIZ[1:0]
C1 C2
$2
$0
C3
$ADDR
A[0]
ATA
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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